1-20
MVS-8000A/8000ASF
<Switch>
S401 (A-5) : MIX-CPU reset switch
Pressing this switch initializes the CPU on the MIX-48A
board.
S2702 (A-5) : Monitor reset switch
The reset switch that is used to reset the monitor during
maintenance through the terminal.
<Slit land>
SL1, SL2 (A-4) and SL3 (A-5) : JTAG chain switching
They are the slit lands that are used to switch the JTAG
chains. Connect these slit lands to open or to close them so
that the following statuses can be obtained.
SL1
SL2
SL3
Status
short
open
open
The chain of CPLD only is
established.
open
short
short
All of the JTAG devices are
connected in chain.
<LED on the CPU-DR module>
Refer to < LED on the CPU-DR module > in “1. CA-54A
board”.
<Switch on the CPU-DR module>
Refer to < Switch on the CPU-DR module > in “1. CA-
54A board”.
<LED on the CPU-DT module>
Refer to <LED on the CPU-DT module> in “1. CA-54A
board”.
<Switch on the CPU-DT module>
Refer to <Switch on the CPU-DT module> in “1. CA-54A
board”.
<LED>
D204, D208, D304 (A-3) :
+
+
+
+
+
1.5 V-1 to 3
+
1.5 V-1 to 3 power supply status indication.
Lit when the
+
1.5 V-1 to 3 power are supplied.
D308 (A-3) :
+
+
+
+
+
2.5 V
+
2.5 V power supply status indication.
Lit when the
+
2.5 V power is supplied.
D409 (A-2) :
+
+
+
+
+
3.3 V
+
3.3 V power supply status indication.
Lit when the
+
3.3 V power is supplied.
D410 (A-2) :
+
+
+
+
+
12 V
+
12 V power supply status indication.
Lit when the
+
12 V power is supplied.
If this LED does not light, the fuse may have blown.
D3701 (A-6) : CONFIG. ERROR status LED
Indicates the configuration error of the FPGA.
If this LED lit, the FPGA can possibly be working incor-
rectly.
D3702, D3704, D3705 (A-6) : C2, C1 and C0 status
LED
Indicates the status of CPU on the circuit board.
D3703 (A-6) : PLL UNLOCK status LED
Indicates lock/unlock of the PLL (Phase Locked Loop) in
the FPGA.
If this LED lit, the PLL can possibly be unlocked.
