54
Pin No.
Pin Name
I/O
Description
63
VSS
—
Ground terminal
64
MD3
I/O
Two-way data bus with the D-RAM (IC507) and CD mechanism controller (IC505)
Data input from the program ROM (IC508)
65
VDD
—
Power supply terminal (+3.3V)
66
MD15
I/O
Two-way data bus with the D-RAM (IC507)
67
VSS
—
Ground terminal
68
MD4
I/O
Two-way data bus with the D-RAM (IC507) and CD mechanism controller (IC505)
Data input from the program ROM (IC508)
69
VDD
—
Power supply terminal (+3.3V)
70
MD10
I/O
Two-way data bus with the D-RAM (IC507)
71
VSS
—
Ground terminal
72
MD5
I/O
Two-way data bus with the D-RAM (IC507) and CD mechanism controller (IC505)
Data input from the program ROM (IC508)
73
MD9
I/O
Two-way data bus with the D-RAM (IC507)
74
MD6
I/O
Two-way data bus with the D-RAM (IC507) and CD mechanism controller (IC505)
Data input from the program ROM (IC508)
75
VDD
—
Power supply terminal (+3.3V)
76
MD8
I/O
Two-way data bus with the D-RAM (IC507) Data output to the program ROM (IC508)
77
VSS
—
Ground terminal
78
MD7
I/O
Two-way data bus with the D-RAM (IC507) and CD mechanism controller (IC505)
Data input from the program ROM (IC508)
79
LDQM
O
Data output to the D-RAM (IC507)
80
UDQM
O
Data output to the D-RAM (IC507)
81
VDD
—
Power supply terminal (+3.3V)
82
MWE
O
Write enable signal output to the D-RAM (IC507)
83
VSS
—
Ground terminal
84
SD-CLK
O
System clock output to the D-RAM (IC507)
85
SD-CAS
O
Column address strobe signal output to the D-RAM (IC507)
86
SD-RAS
O
Row address strobe signal output to the D-RAM (IC507)
87
VDD
—
Power supply terminal (+3.3V)
88
SD-CS1
O
Not used (open)
89
VSS
—
Ground terminal
90
SD-CS0
O
Chip select signal output to the D-RAM (IC507)
91
VSS
—
Ground terminal
92
EDO-CAS
O
Not used (open)
93
VSS
—
Ground terminal
94
EDO-RAS
O
Not used (open)
95
VDD
—
Power supply terminal (+3.3V)
96
MA9
O
Address signal output to the D-RAM (IC507) and program ROM (IC508)
97
VSS
—
Ground terminal
98 to 100
MA7, MA8, MA10
O
Address signal output to the D-RAM (IC507) and program ROM (IC508)
101
VDD
—
Power supply terminal (+3.3V)
102
MA7
O
Address signal output to the D-RAM (IC507) and program ROM (IC508)
103
VSS
—
Ground terminal
104 to 106
MA0, MA6, MA1
O
Address signal output to the D-RAM (IC507) and program ROM (IC508)
107
VDD
—
Power supply terminal (+3.3V)
108
MA5
O
Address signal output to the D-RAM (IC507) and program ROM (IC508)
109
VSS
—
Ground terminal
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