56
Pin No.
141
142,143
144
145
146
147
148
149
150
151
152
153
154,155
157
158
160
161
162
166
167
168
169
180
181
182
183
184
185
190
I/O
I/O
O
-
O
-
I/O
O
-
O
-
O
I/O
O
I/O
I/O
-
O
-
O
O
-
I/O
I
-
I
-
I
I
I/O
Description
Programmable I/O pins.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
3.3-V supply voltage for core logic and I/O signals.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Ground for core logic and I/O signals.
Programmable I/O pins.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
3.3-V supply voltage for core logic and I/O signals.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Ground for core logic and I/O signals.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Programmable I/O pins.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after the falling (active) edge
of HSYNC.
Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the first HSYNC after the
falling edge of VSYNC. VSYNC can accept vertical synchronization or top/bottom field notification from an
external source. (VSYNC HIGH=bottom field. VSYNC LOW=Top field)
3.3-V supply voltage for core logic and I/O signals.
Serial audio samples relative to DA-BCK clock.
Ground for core logic and I/O signals.
PCM left-right colck. Identifies the channel for each audio sample. the polarity is programmable.
PCM bit clock. Divided by 8 form DA-XCX, DA-BCK can be either 48 or 32 times the sampling clock.
3.3-V supply voltage for core logic and I/O signals.
Audio external frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK can be either 384 or 256
times the sampling frequency.
Ground for core logic and I/O signals.
PCM input data, two channels. Serial audio samples relative to DA-BCK clock, resulting in downmixed audio output.
3.3-V supply voltage for core logic and I/O signals.
3.3-V analog supply voltage.
Video clock. Clocks out data on input. VDATA[7:0]. Clock is typically 27 MHz.
System clock. Decoder requires an external 27MHz TTL oscillator. Drive with the same 27-MHz as VCK.
Serial CD data.
3.3-V supply voltage for core logic and I/O signals.
Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH).
Ground for core logic and I/O signals.
CD bit clock. Decoder accept multiple BCK rates.
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture on-screen until the next valid
picture is decoded.
Programmable I/O pins.
Pin Name
PIO[10:0]
VDATA[7:0]
VDD
VDATA[7:0]
VSS
PIO[10:0]
VDATA[7:0]
VDD
VDATA[7:0]
VSS
VDATA[7:0]
PIO[10:0]
VDATA[7:0]
HSYNC
VSYNC
VDD
DA-DATA
VSS
DA-LRCK
DA-BCK
VDD
DA-XCX
CD-DATA
VDD
CD-LRCK
VSS
CD-BCK
CD-C2PO
PIO[10:0]
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