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46
HCD-CPX22/NXM3
Pin No.
Pin Name
I/O
Description
1
XVss
–
Ground
2
Vsubc
–
Ground
3
VssR
–
Ground
4
OUTR2
O
PWM2 output for R-ch power stage.
5
VddR
–
Power 3.3v)
6
OUTR1
O
PWM1 output for R-ch power stage.
7
VssR
–
Ground
8
VssL
–
Ground
9
OUTL2
O
PWM2 output for L-ch power stage.
10
VddL
–
Power 3.3v)
11
OUTL1
O
PWM1 output for R-ch power stage.
12
VssL
–
Ground
13
XOVss
–
Ground
14
XfsoOUT
O
Secondary master clock buffer output
15
XOVdd
–
Power 3.3v)
16
DVdd
–
Power supply(power supply for digital s1.8v)
17
DVss
–
Ground
18
NSPMUTEI
I
PWM duty50% mute and delta/sigma registor clear signal input
19
SoftMUTE
I
Soft mute signal input
20
PGMUTE
I
Mute signal input for PWM output data
21
SCDT
I
Serial control data input
22
SCSHIFT
I
Serial control shift clock input
23
SCLATCH
I
Serial control latch signal input
24
OVFFLAG
O
R-ch arithmetic section overflow detect flag output
25
OVFFLAG
O
L-ch arithmetic section overflow detect flag output
26
SFLAG
O
Anti-synchronize detect flag output
27
INIT
I
Initalise signal input (power reset)
28
MCKSEL
I
Secondary master clock select input
29
LRCK
I
Sampling clock input (correspond to CD/MD/DVDaudio etc)
30
BCK
I
Bit clock input(correspond to CD/MD/DVDaudio etc)
31
DATA
I
Audio data input(correspond to CD/MD/DVDaudio etc)
32
BFVdd
–
Power 3.3v)
33
BFVss
–
Ground
34
TEST
I
Test terminal(normaly ground)
35
DVdd
–
Power supply(power supply for digital s1.8v)
36
XFfsilN
I
Primary master clock input
37
FsoCKO
O
Secondary fso clock M-output
38
Fsol
I
Secondary fso clock input
39
HPOUTR2
O
Not used
40
HPVssR
–
Ground
41
HPOUTR1
O
Not used
42
HPVddR
–
Power 3.3v)
43
HPOUTL2
O
Not used
44
HPVddL
–
Ground
45
HPOUT
O
Not used
46
HPVddL
–
Power 3.3v)
47
XVdd
–
Power 3.3v)
48
XfsoIN
I
Secondary master clock input(1024/512fso)
• IC705 CXD9788AR (DATA CONTOL) (S-MASTER Board)