Sony DVP-K56P, Руководство по обслуживанию

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5-2
DVP-NS15/NS51P/NS43P/NS53P/K56P
Pin No. Pin name Type Function
4 9 HA3 Output PU Host address bit 3
5 0 HA4 Output PU Host address bit 4
5 1 HA5 Output PU Host address bit 5
5 2 HA6 Output PU Host address bit 6
5 3 HA7 Output PU Host address bit 7
5 4 HA8 Output PU Host address bit 8
5 5 HA18 Output PD, SMT Host address bit 18
5 6 DVSS Ground Ground pin for internal digital circuitry
5 7 HA19 Output PD, SMT Host address bit 19
5 8 DVDD3 Power 3.3V power pin internal digital circuitry
5 9 XWR Output PU, SMT Write enable, active low
6 0 HA16 Output PU Host address bit 16
6 1 DVDD3 Power 3.3V power pin internal digital circuitry
6 2 HA15 Output PU Host address bit 15
6 3 HA14 Output PU Host address bit 14
6 4 HA13 Output PU Host address bit 13
6 5 HA12 Output PU Host address bit 12
6 6 HA11 Output PU Host address bit 11
6 7 HA10 Output PU Host address bit 10
6 8 HA9 Output PU Host address bit 9
6 9 HA20 Output PU, SMT Host address bit 20
7 0 XROMCS Output SMT Chip select (Active low)
7 1 DVSS Ground Ground pin for internal digital circuitry
7 2 HA1 Output PU Host address bit 1
7 3 XRD Output SMT Read enable, active low
7 4 DVSS Ground Ground pin for internal digital circuitry
7 5 HDD Output Host address bit 0
7 6 HD1 Output Host address bit 1
7 7 HD2 Output Host address bit 2
7 8 HD3 Output Host address bit 3
7 9 HD4 Output Host data bit 4
8 0 HD5 Output Host data bit 5
8 1 HD6 Output Host data bit 6
8 2 LIMITSW Input PD, SMT BU limit switch sensor input
8 3 ALE Output PU, SMT Address latch enable
8 4 DVDD18 Power 1.8V power pin for internal digital circuitry
8 5 HD7 Output Host data bit 7
8 6 HA17 Output PU Host address bit 17
8 7 DVDD3 Power 3.3V power pin for internal digital circuitry
8 8 HA0 Output PU Host address bit 0
8 9 UWR# Output PU, SMT 8032 write strobe
9 0 URD# Output PU, SMT 8032 read strobe
9 1 IFBSY Input PU, SMT Ext CPU ready/busy interrupt signal (H: Busy, L: Ready)
9 2 IFCK Output PU, SMT Ext CPU serial clock
9 3 EEWP Output PU, SMT EEPROM write protect control (H: WP enable, L: WP disable)
9 4 XIFCS Output, PU SMT Chip select for Ext CPU (Active low)
9 5 IFSDI Input PU, SMT Ext CPU serial data input
9 6 SCL In/Out PU, SMT Hardware IIC clock
9 7 DVSS Ground Ground pin for internal digital circuitry
9 8 SDA In/Out PU, SMT Hardware IIC data
9 9 TSD_M Input PU, SMT Motor driver thermal shutdown sensor (Active low)
100 IFSDO Output PU, SMT Ext CPU serial data output
101 RXD Input PU, SMT Hardware RS232C RXD
102 TXD Output PU, SMT Hardware RS232C TXD