Sony DVP-CX985V, Руководство по обслуживанию, Страница: 119 / 150

119
DVP-CX985V
• MB BOARD IC905 CXD2753R (DSD DECODER)
Pin No. Pin Name I/O Description
1 VSC —
Ground terminal (for core)
2 XMSLAT I
Chip select signal input from the system controller
3 MSCK I
Serial clock signal input from the system controller
4 MSDATI I
Serial data input from the system controller
5 VDC —
Power supply terminal (+2.5V) (for core)
6 MSDATO O
Serial data output to the system controller
7 MSREADY O
Ready signal output to the system controller
8 XMSDOE O
Serial data output enable signal output terminal Not used
9 XRST I
Reset signal input from the system controller “L”: reset
10 SMUTE I
Soft muting control signal input from the system controller
11 MCKI I
Master clock signal (33.8688 MHz) input from the clock generator
12 VSIO —
Ground terminal (for I/O)
13, 14
EXCKO1,
EXCKO2
O External clock signal output terminal Not used
15 LRCK O
L/R sampling clock signal output terminal Not used
16 FRAME O
Not used
17 VDIO —
Power supply terminal (+3.3V) (for I/O)
18 to 21 MNT0 to MNT7 O
Monitor signal output terminal Not used
22 to 25 TEST0 I
Input terminal for the test (normally: fixed at “L”)
26 TCK I
Clock signal input terminal
27 TDI I
Serial data input from the DSP
28 VSC —
Ground terminal (for core)
29 TDO O
Serial data output to the audio DSP
30 TMS I
Selection signal input terminal
31 TRST I Reset signal input from the interface controller “L”: reset
32 to 34 TEST1 to TEST3 I Input terminal for the test (normally: fixed at “L”)
35 VDC — Power supply terminal (+2.5V) (for core)
36 TESTO O Output terminal for the test
37 XBIT O Not used
38 to 41
SUPDT0 to
SUPDT3
O Supplementary data output terminal Not used
42 VSIO — Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O Supplementary data output terminal Not used
45 VDIO — Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O Supplementary data output terminal Not used
48 XSUPAK O Supplementary data acknowledge signal output terminal Not used
49 VSC — Ground terminal (for core)
50 DSAEXR O Not used
51, 52 TESTI I Input terminal for the test (normally: fixed at “L”)
53 TESTO O Output terminal for the test
54 VDC — Power supply terminal (+2.5V) (for core)
55 DSADML O DSD data output for L-ch down mix to the D/A converter
56 DSADMR O DSD data output for R-ch down mix to the D/A converter
57 BCKASL I
Input/output selection signal input terminal of bit clock signal for DSD data output
“L”: input (slave), “H”: output (master) Fixed at “H” in this set