Sony DVP-CX985V, Руководство по обслуживанию, Страница: 117 / 150

117
DVP-CX985V
• MB BOARD IC701 CXD9705R (MECHANISM CONTROLLER)
Pin No. Pin Name I/O Description
1 HD15 I/O
Two-way data bus terminal
2 VSS —
Ground terminal
3 to 9 HD14 to HD8 I/O
Two-way data bus terminal
10, 11
HA19, HA4
O
Address signal output terminal
12 VSS —
Ground terminal
13 to 16
HA3 to HA0
O
Address signal output terminal
17 XGAIT O
Interrupt signal output to the system controller
18 XWR I
Write enable signal input from the system controller
19 XRD I
Read enable signal input from the system controller
20 XGACS I
Chip select signal input from the system controller
21 WOBBLE I
Not used
22 ADVDD —
Power supply terminal (+3.3V)
23 VSS —
Ground terminal
24 CPUCK I
Master clock (33 MHz) input from the system controller
25 TSENS2 I
Table position sensor 2 input terminal
26 TSENS4 I
Table position sensor 4 input terminal
27 LD_IN I
Loading detect switch input terminal “L”: loading in
28 LD_OUT I
Loading detect switch input terminal “L”: loading out
29 LOCK I
Lock detect switch input terminal “L”: lock
30 TSENS3 I
Table position sensor 3 input terminal
31 TSENS1 I
Table position sensor 1 input terminal
32 (NC) I
Not used
33 VDD —
Power supply terminal (+3.3V)
34 XRST I
Reset signal input from the system controller “L”: reset
35 VPD —
Not used
36 POPUP I
Pop detect switch input terminal “L”: pop up
37 POPDOWN I
Pop detect switch input terminal “L”: pop down
38 DR_OP I Door detect switch input terminal “L”: door open
39 DR_CLS I
Door detect switch input terminal “L”: door close
40 ADVDD2 —
Power supply terminal (+3.3V)
41 TRST I
Reset signal input from the interface controller “L”: reset
42 VSS —
Ground terminal
43 TCK I
Clock signal input terminal
44 TMS I
Mode selection signal input terminal
45
TDI
I
Serial data input terminal
46 NFBUSY I
Busy signal input from the nand flash memory
47 ADVDD3 —
Power supply terminal (+3.3V)
48 NFCE O
Chip enable signal output to the nand flash memory
49 NFCLE O
Command latch enable signal output to the nand flash memory
50 NFALE O
Address latch enable signal output to the nand flash memory
51 NFWP O
Write protect signal output to the nand flash memory
52 VSS —
Ground terminal
53 NFRE O
Read enable signal output to the nand flash memory
54 NFWE O
Write enable signal output to the nand flash memory
55 NFTEST O
Test mode selection signal output to the nand flash memory