DSX-MS60
DSX-MS60
17
17
4-8. SCHEMATIC DIAGRAM - MAIN Section (5/5) -
• See page 23 for IC Block Diagrams.
(1/5)
5
MAIN
BOARD
7
(3/5)
BOARD
MAIN
IC B/D
0
0
3.1
3.1
8.3
0.4
3.8
3.8
0.7
3.6
4
0.7
6
6
8.3
0
0
0
8.3
2.2
4.5
5.6
8.3
7
3.9
3.1
3.1
1000p
C5
TU_RCH
560uH
L8
3.3uH
L1
FB4
FB1
I2C_SCK
L2
2.2uH
1
C15
VSM
VR1
TU_LCH
1
C14
C32
10p
J1
GND_1
8.5V
16V
47
C28
33k
R10
560uH
L7
FB3
FB2
I2C_SIO
1 AMRFIN
2 AMRFDEC
3 FMIN2
4 FMIN1
5 GNDRF
6 VCC2
7 AMRFAGC
8 LOUT
9 ROUT
10 GNDAUD
11 AMIFAGC2
12 MPXIN
13 MPXOUT
14 RSSI
15 XTAL2
16 XTAL1
17
GNDD
18
SCL
19
SDA
20
VREF
21
VREGSUP
22
VCC1
23
GND
24
VCODEC
25
PLL
26
PLLREF
27
TEST
28
AMSELIN1
29
AMSELIN2
30
AMIFAGC1
31
AMSELOUT1
32
AMSELOUT2
4MHz
X1
FM MIX
L6
1
2
3
4
6
2.2
C13
0.1
C17
0.22
C12
0.47
C16
68k
R6
12p
C18
0.1
C9
470k
R2
470k
R1
1000p
C1
0.1
C26
0.1
C27
0.01
C20
0.01
C22
1
C21
0.1
C24
0.01
C23
0.1
C25
22
R12
100
R14
100
R13
4.7k
R11
0.01
C19
15p
C6
33p
C8
IC1
PLL
MAIN BOARD (5/5)
CAM002
(CHASSIS)
ANTENNA
IN
TEF6617T/V1/S470, 518
IC1
E
3
D
F
7
A
C
4
2
6
B
5
1
(Page 13)
(Page 15)