4-8
CA-755/755P
IC
C-MOS DIGITAL LINE MEMORY
—TOP VIEW—
NC
NC
V
DD (+5V)
V
DD (+5V)
NC
NC
NC
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
I/O
I
I
I
I
I
—
I
I
I
I
I
I
SIGNAL
D0
D1
D2
D3
D4
GND
D5
D6
D7
D8
D9
TINT
I
I
I
I
I
I
—
I
I
I
I
I
PSW7
PSW6
PSW5
PSW4
PSW3
PSW2
V
DD
PSW1
PSW0
PSB2
PSB1
PSB0
I
O
O
O
O
—
O
O
O
O
O
O
OEN
DOT9
DOT8
DOT7
DOT6
GND
DOT5
DOT4
DOT3
DOT2
DOT1
DOT0
(V
DD
= +5V)
—
—
I
I
I
I
—
—
—
—
—
—
N.C
N.C
AEN
N/P
SCLK
CLK
V
DD
N.C
N.C
N.C
N.C
N.C
24
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DOT0
DOT1
DOT2
DOT3
DOT4
DOT5
DOT6
DOT7
DOT8
DOT9
OEN
PSB0
PSB1
PSB2
PSW0
PSW1
PSW2
PSW3
PSW4
PSW5
PSW6
PSW7
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
GND
GND
SCLK
TINT
AEN
N/P
8
9
10
11
12
2
3
4
5
7
8
9
10
11
36
35
34
33
32
31
29
28
27
26
21
20
18
25
24
23
22
17
16
15
14
13
42
41 12 39 40
PIN
NO.
13
14
15
16
17
18
19
20
21
22
23
24
I/O SIGNAL
PIN
NO.
25
26
27
28
29
30
31
32
33
34
35
36
I/O SIGNAL
PIN
NO.
37
38
39
40
41
42
43
44
45
46
47
48
I/O SIGNAL
C-MOS PULSE GENERATOR
- TOP VIEW -
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DD
V (+5.0V)
GND
PIN
No.
I/O
SIGNAL
SIGNAL
I/O
No.
PIN
SIGNAL
I/O
No.
PIN
SIGNAL
I/O
No.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
–
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–
O
I
O
O
O
I01
I02
I03
I04
I05
I06
I07
I08
MODE
I09
I10
I11
I12
I13
I14
I15
GND
A19
I17
RST
CKH
TES2
TEST
OT00
OT01
OT02
OT03
OT04
OT05
OT06
OT07
OT08
OT09
OT10
OT11
OT12
OT13
OT14
OT15
CLK
OT16
RAM
ROM
V
DD
(V =+5.0V)
DD
I01–I17
RST
OT00-OT16
; INPUT
; RESET
; OUTPUT
MODE
; MODE SELECT
(H:WINDOW GEN / L:CHIP SELECT LOGIC)
A19
; ADDRESS INPUT
CKH
INPUT
; FOR TEST
CLK
; CLOCK
TES2
; FOR TEST
TEST
; FOR TEST
OUTPUT
RAM
; RAM OUT
ROM
; ROM OUT
CXD8344AQ (SONY)
9
MODE
WINDOW /
1-8
I01–I08
I09–I15
10-16
A4-A19
CHIP
SELECT
LOGIC
INPUT
SELECTOR
AS
RAM
43
RAM
ROM
44
ROM
24-32
OT00-OT08
IO9-IO15
EE PROM
OUTPUT
SELECTOR
WINDOW
GEN
DT0-DT7
MAD
WRB
CSB
HD
VD
N/P
GM O
SU WO
AI WO
TESG
19
I17
f
H
GEN &
CLOCK
BUFFER
FH
M9
M18
M18B
CLK
41
RST
20
CKH
21
TES2
22
TEST
23
33-38
OT09-OT14
OT15
40
OT16
42
CHIP SELECT
FH M1
FH M2
/
3
/
8
/
8
/
16
/
7
/
9
/
6
/
7
18
A19
(at MODE "L")
(at MODE "H")
IO0-IO8
CXK1203AR (SONY)
CXK1203AR-T4
AEN
CLK
DIN0-DIN9
DOT0-DOT9
N/P
OEN
PSB0-PSB2
PSW0-PSW7
SCLK
TINT
LINE MEMORY SELECT
CLOCK
VIDEO DATA INPUT
VIDEO DATA OUTPUT
NTSC/PAL/SECAM SELECT
OUTPUT ENABLE
DELAY STEP SELECT (1 BITxN)
DELAY STEP SELECT (8 BITxN)
CLOCK EDGE SELECT
TEST
;
;
;
;
;
;
;
;
;
;
1-5
7-11
13-18
20, 21
N/P
40
AEN
39
BUFF
26-29
31-36
25
22-24
42
41
12
TINT
SCLK
CLK
OEN
1 LINE MEMORY
(1138 x 10bit)
ADDRESS
COUNTER
ADDRESS
MULTIPLEXER
TIMING
CONTROLLER
SMALL DELAY
CONTROLLER
DIN0
DIN9
—
DOT0
DOT9
—
PSB0
PSB2
—
PSW0
PSW7
—
BUFF
Содержание CA-755
Страница 4: ......
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Страница 92: ......
Страница 98: ...5 6 CA 755 755P 5 6 RX 37 Block Diagram Block Diagram RX 37 RX 37 CA 755 CA 755P ...
Страница 100: ......
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Страница 107: ...6 9 CA 755 755P 6 9 MB 705 MB 705 MB 705 A SIDE 1 663 948 11 MB 705 B SIDE 1 663 948 11 CA 755 UC CA 755 J CA 755P CE ...
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Страница 111: ...7 1 CA 755 755P 7 1 2 3 4 5 1 I J K L M N O P Section 7 Schematic Diagrams ...
Страница 126: ...7 16 CA 755 755P 7 16 2 3 4 5 A B C D E F G H 1 ...
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