
Developer's Board Manual Rev A
Page 3 of 28
SEM/CX-02:0061/MAN
List of Tables
T
ABLE
1: D
EVELOPER
'
S
K
IT
C
ONTENT
L
IST
................................................................................................................................. 6
T
ABLE
2: B
ASELINE
J
UMPER
S
ETTINGS FOR
DM-15/25 ............................................................................................................. 12
T
ABLE
3: B
ASELINE
D
IP
S
ETTINGS FOR
DM-15/25 .................................................................................................................... 12
T
ABLE
4: B
ASELINE
J
UMPER
S
ETTINGS FOR
CM-4
X
.................................................................................................................. 12
T
ABLE
5: B
ASELINE
D
IP
S
ETTINGS FOR
CM-4
X
......................................................................................................................... 12
T
ABLE
6: B
ASELINE
J
UMPER
S
ETTINGS FOR
DM-10/20 ............................................................................................................. 12
T
ABLE
7: B
ASELINE
D
IP
S
ETTINGS FOR
DM-10/20 .................................................................................................................... 12
T
ABLE
8: D
ESCRIPTION OF
C
ONNECTORS
, S
WITCHES AND
I
NDICATORS
..................................................................................... 19
T
ABLE
9: VDIG H
EADER
S
ETTINGS
(X103) .............................................................................................................................. 19
T
ABLE
10: VCC H
EADER
S
ETTINGS
(X104) .............................................................................................................................. 20
T
ABLE
11: V
OLTAGE LEVELS FOR EACH MODULE FAMILY
......................................................................................................... 20
T
ABLE
12: J
UMPER SETTINGS FOR EACH MODULE FAMILY
......................................................................................................... 20
T
ABLE
13: VREF H
EADER
S
ETTINGS
(X101) ............................................................................................................................ 20
T
ABLE
14: D
ESCRIPTION OF
O
PERATION
M
ODE
S
WITCH
S
ETTINGS
........................................................................................... 20
T
ABLE
15: M
ODULE
ON S
TATE
................................................................................................................................................. 21
T
ABLE
16: RS-232 DB9 P
IN
-
OUT
.............................................................................................................................................. 21
T
ABLE
17: RS-232 DB9 J22 R
OUTING
...................................................................................................................................... 21
T
ABLE
18: H
EADER
X102 S
ETTINGS
(J22-DCD) ....................................................................................................................... 21
T
ABLE
19: S3 S
ETTINGS TO ENABLE
HW F
LOW
C
ONTROL
........................................................................................................ 22
T
ABLE
20: S3 S
ETTINGS TO DISABLE
HW F
LOW
C
ONTROL
....................................................................................................... 22
T
ABLE
21: D
IRECTION OF
S
ERIAL
D
ATA
S
IGNALS
...................................................................................................................... 22
T
ABLE
22: P
IN
-
OUT OF
S
YSTEM
C
ONNECTOR
H
EADER
.............................................................................................................. 23
List of Figures
F
IGURE
1: E
XPLODED VIEW DRAWING OF DEVELOPER
'
S BOARD WITH
DM-15/25 ........................................................................ 7
F
IGURE
2: E
XPLODED VIEW DRAWING OF DEVELOPER
'
S BOARD WITH HEAT SINK
......................................................................... 8
F
IGURE
3: E
XPLODED VIEW DRAWING OF DEVELOPER
'
S BOARD WITH
CM-4
X
.............................................................................. 9
F
IGURE
4: DM-
XX
C
ONNECTION
D
IAGRAM
............................................................................................................................... 10
F
IGURE
5: CM-4
X
C
ONNECTION
D
IAGRAM
................................................................................................................................ 11
F
IGURE
6: A
SSEMBLE
D
RAWING OF
D
EVELOPER
'
S
B
OARD
(R
EVISION
P1F)............................................................................... 15
F
IGURE
7: A
SSEMBLE
D
RAWING OF
D
EVELOPER
'
S
B
OARD
(R
EVISION
P1E) .............................................................................. 16
F
IGURE
8: A
SSEMBLE
D
RAWING OF
D
EVELOPER
'
S
B
OARD
(R
EVISION
P1D) .............................................................................. 17
Revision History
Release
Date
Summary of Changes
A
5/17/02
Initial Release - JPL