SONIX SN32F755, Руководство пользователя

Страница: 61 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 61
Version 2.0
3.4.4 APB Clock Prescale register 2 (SYS1_APBCP2)
Address Offset: 0x0C
Bit Name Description Attribute Reset
31:4 Reserved R 0
3:0 CLKOUTPRE[3:0]
Clock-out source prescaler
0000: Clock-out source / 1
0001: Clock-out source / 2
0010: Clock-out source / 4
0011: Clock-out source / 8
0100: Clock-out source / 16
0101: Clock-out source / 32
0110: Clock-out source / 64
0111: Clock-out source / 128
1000: Clock-out source / 256
1001: Clock-out source / 512
Other: Reserved
R/W 0
3.4.5 Peripheral Reset register (SYS1_PRST)
Address Offset: 0x10
All bits are cleared by HW automatically after setting as “1”.
Bit Name Description Attribute Reset
31:25
Reserved R 0
24 WDTRST
WDT reset
0: No effect
1: Reset WDT
R/W 0
23 RTCRST
RTC reset
0: No effect
1: Reset RTC
R/W 0
22
I2SRST
I2S reset
0: No effect
1: Reset I2S
R/W 0
21
I2C0RST
I2C0 reset
0: No effect
1: Reset I2C0
R/W 0
20
I2C1RST
I2C1 reset
0: No effect
1: Reset I2C1
R/W 0
19:18 Reserved R 0
17 USART1RST
USART1 reset
0: No effect
1: Reset USART1
R/W 0
16 USART0RST
USART0 reset
0: No effect
1: Reset USART0
R/W 0
15
LCDRST
LCD reset
0: No effect
1: Reset LCD
R/W 0
14 Reserved R 0
13 SSP1RST
SSP1 reset
0: No effect
1: Reset SSP1
R/W 0