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Rev. 0.8
To send the TX_TUNE_FREQ command and arguments, the system controller sends the START condition,
followed by the 8-bit control word, which consists of a seven-bit device address (0010001b SEN = 0 or 1100011b
SEN = 1) and the write bit (0b) indicated by ADDR+W = 00100010b = 0x22. In this example, SEN = 0 resulting in
the control word ADDR+W = 00100010b = 0x22. If instead SEN = 1, the resulting control word would be
ADDR+W = 11000110b = 0xC6. The device acknowledges the control word by setting SDIO = 0, indicated by
ACK = 0. The system controller then sends the CMD byte, 0x30, and again the device acknowledges by setting
ACK = 0. The system controller and device repeat this process for the ARG1, ARG2, and ARG3 bytes. Commands
may take up to seven argument bytes, and this flexibility should be designed into the 2-wire bus mode
implementation. Alternatively, all seven argument bytes may be sent for all commands, but unusual arguments
must be 0x00.
Unpredictable device behavior will result if more than seven arguments are sent.
To read the status and response from the device, the system controller sends the START condition, followed by the
eight-bit control word, which consists of the seven bit device address and the read bit (1b). In this example,
SEN = 0 and the write control word is ADDR+R = 00100011b = 0x23. If SEN = 1, the write control word would be
ADDR+R = 11000111b = 0xC7. The device acknowledges the control word by setting ACK = 0. Next the system
controller reads the STATUS byte. In this example, the STATUS byte is 0x00, indicating that the CTS bit, bit 8, has
not been set. The response bytes are not ready for reading and that the device is not ready to accept another
command. The system controller sets SDIO = 1, indicated by NACK = 1, to signal to the device the 2-wire transfer
will end. The system controller should set the STOP condition. This process is repeated until the STATUS byte
indicates that CTS bit is set, 0x80 in this example.
When the STATUS byte returns CTS bit set, 0x80 in this example, the system controller may read the response
bytes from the device. The controller sets ACK = 0 to indicate to the device that additional bytes will be read. The
RESP1 byte is read by the system controller, followed by the system controller setting ACK = 0. This is repeated
for RESP2. RESP3 is read by the system controller followed by the system controller setting NACK = 1, indicating
that RESP3 is the last byte to be read. The system controller then sets the STOP condition. Responses may be up
to 15 bytes in length (RESP1–RESP15) depending on the command. It is acceptable to read all 15 response bytes.
However, unused response bytes return random data and must be ignored. Note that the TX_TUNE_FREQ
command returns only the STATUS byte and response bytes are shown only for completeness.
START
ADDR+W
ACK
CMD
ACK ARG1 ACK
ARG2
ACK
ARG3
ACK
STOP
START
0x22
0
0x30
0
0x00
0
0x27
0
0x7E
0
STOP
START
ADDR+R
ACK
STATUS
NACK
STOP
START
0x23
0
0x00
1
STOP
START ADDR+R
ACK
STATUS
ACK
RESP1
ACK
RESP2
ACK
RESP3 NACK STOP
START
0x23
0
0x80
0
0x00
0
0x00
0
0x00
1
STOP
