©2018
Rev 1.1
13
Functional Description
that the signal level starts off higher as it enters the first mixer as well as subsequent components such
that the apparent linearity of the device is lower.
To set the device for better linearity, the gain should be shifted to the output IF path, after the mixer, and
reducing the gain in the RF path. The signal power level at the first mixer should be lower than -20 dB for
improved linearity. Since the input signal is low, the relative SNR will be lower. But, as the first mixer and
subsequent components experience lower power levels, the apparent linearity of the device is improved.
When the device gain is balanced well, the device could achieve SNR of better than 130 dBc/Hz while
maintaining IMD3 levels close to 75 dBc. These numbers are representative of converters used in large
box high end spectrum analyzers. When the device is optimized for best SNR, typical numbers > -150
dBc/Hz can be achieved, and when the device is optimized for sensitivity, the input spectral noise floor is
typically lower than -165 dBm/Hz. The flexible use of these attenuators and pre-amplifier allows the
downconverter to achieve better than 190 dB of measurement dynamic range.
The LO Synthesizer and External Ports
The internal LO synthesizer is a hybrid between integer-N PLL and DDS, enabling it to tune at 1 Hz step
while maintaining low phase noise. The reference signal for the generation of the LO signal comes from
an internal temperature-controlled crystal oscillator (TCXO).
Figure 5. Block diagram of the local oscillator
The Reference Clocks
The base clock of the downconverter is a 10 MHz voltage-controlled temperature-controlled crystal
oscillator (VCTCXO) with initial accuracy of better than 500 ppb once the device has reached a stable
temperature. Its initial accuracy is set at the factory via an on-board 14-bit voltage reference DAC. This
DAC is accessible for dynamic accuracy calibration. The other reference is a 100 MHz voltage-controlled
crystal oscillator (VCXO), which is phase locked to the base reference whenever an external reference
source is not used.
When an external reference is selected as the base clock by enabling the device to phase lock to it, the
effect only occurs when the presence of this reference is detected. In other words, although the device is
programmed to lock externally it will not attempt to do so until the reference signal is detected at the
input reference port. Notice, both the reference clocks (TCXO and VCXO) will attempt to lock to the
external source. Having the VCXO lock directly to the external source has the advantage of utilizing the
close-in phase noise of the source; it is best to assume that the external source is superior to the internal
base. Although the internal VCTCXO is not used when an external reference is selected, it is important to
100M PLL
REF DETECT
ENABLE
LO
TCXO PLL
LO/
Ref In
To
Mixer
To
Mixer