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CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Don't change this field from
the default value specified by the system designer.
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The Choice: 1, 1.5, 2, 2.5, 3, 3.5 or 4.
DRAM RAS# to CAS# Delay
This field lets you insert a timing delay between the CAS and RAS strobe
signals, and you can use it when DRAM is written to, read from, or re-
freshed. Faster performance is gained in high speed, more stable perfor-
mance, in low speed. This field is applied only when synchronous DRAM
is installed in the system.
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The Choice: 1, 2, 3 or 4.
DRAM RAS# Precharge
If an insufficient number of cycles is allowed for the RAS to accumulate its
charge before DRAM refresh, the refresh may be-incompleted, and the
DRAM may fail to retain data. Fast gives faster performance; and Slow
gives more stable performance. This field is applied only when synchro-
nous DRAM is installed in the system.
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The Choice: 1, 2, 3 or 4.
Active to Precharge Delay
The precharge time is the number of cycles it takes for DRAM to accumu-
late its charge before refresh.
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The Choice: 1, 2, 3, 4, 5, 6, 7, or 8.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When
this area is reserved, it can't be cached. The user information of peripher-
als that need to use this area of system memory usually discusses their
memory requirements.
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The Choice: Enabled or Disabled.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h~FFFFFh, resulting in better system performance. However, if any
program is written to this memory area, a system error may result.
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The Choice: Enabled or Disabled.
Spectrum Spreading Amount
This item allows you to set the spectrum spreading amount.
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The Choice : 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%, 1.75%,
or Disabled.
