Shivaki STV-24LEDGR7, Руководство по обслуживанию

Страница: 80 / 175

Figure 6. Data Output (Read) Timing
Figure 5. Data Input (Write) Timing
K4T51163QI
datasheet
DDR2 SDRAM
Rev. 1.0
K4T51083QI
K4T51043QI
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V
REF
. In differential mode, these
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to V
SS
through a 20
Ω
to 10 k
Ω
resistor to insure proper operation.
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to V
SS
.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
tDS tDH
tWPRE tWPST
tDQSH tDQSL
DQS
DQS
D
DMin
DQS
DQ
DM
tDH
DMin
DMin
DMin
D D D
DQS
V
IL
(AC)
V
IH
(AC)
V
IL
(AC)
V
IH
(AC)
V
IL
(DC)
V
IH
(DC)
V
IL
(DC)
V
IH
(DC)
tDS
tCH tCL
CK
CK
CK/CK
DQS/DQS
DQ
DQS
DQS
tRPST
Q
tRPRE
tDQSQ(max)
tQH
tQH
tDQSQ(max)
Q
Q Q
Page 64 of 152