Sharp QD-101MM, Руководство по обслуживанию

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Fig. 5 Audio Input Circuit Block Diagram
5. PLL CIRCUIT
The dot clock (VCOIN) is generated by the PLL circuit shown in Fig.6. The dot clock is necessary
to sample the video signal from the computer and change it into the suitable dot data.
Hsync signal from computer enters into IC100. This signal is compared frequency and phase
with the feed-back signal, which is generated from VCOIN by the phase comparator in IC100.
If any error of phase or frequency occurs between Hsync and VCOIN, LOW or HIGH level is
output at PBD of IC100, and when both frequency and phase agree with each other, high
impedance is output.
The output signal from the PDB terminal is converted into a DC voltage by a loop filter and then
controls the VCO.
To select the high band or low band, either VCO is selected according to the signals from No.
120 pin and No. 119 pin of IC100.
SMUTE
VOLUME
PHONE JACK STEREO INPUT
AUDIO
LEVEL
CONTOROLLER
MUTE SW
AMPLIFIER
SPEAKER
SPEAKER
AMPLIFIER
ADJUST
CN502
IC500
TA8184F
SP500
IC503
TDA1905
VR501
1
2
2
7
24
5
4