Sharp QD-101MM, Руководство по обслуживанию

Страница: 16 / 66

15
RESET
signal
V
S1
(4.5V)
V
CPU
V
HYS1
(15mV)
T
PO
T
PO
T
PO
POWER OFF
DETECTION
signal
V
S2
(4.15V)
V
CC
V
HYS2
(200mV)
Fig.8
Fig.9
When the power is turned on, V
LCD
, V
CC
and V
CPU
rise. If V
CPU
exceeds V
S1
+V
HYS1
, the RESET
signal is shifted to “High” level at the timing shown in Fig. 10. The reset operation of IC400 is
canceled and executes the program.
When the power is turned off, the power OFF detection signal is shifted to “Low” when V
CC
and
V
LCD
drops sharply below V
S2
.
On the other hand, Vcpu is backed up by C425 (220mF) so that it can maintain 4.5V for the time
of TW after the trailing edge of the power OFF detection signal. See Fig. 11. (TW is the time
for IC400 to retreat the data to EEPROM.) If V
CPU
drops below V
S1
, the RESET signal level is
shifted to “Low”, and IC400 starts resetting.