Sharp LC-40LE730E, Руководство по обслуживанию

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LC-40LE730
LC-46LE730
• IC 3701 : FRC
Part number: ZR39301BGCG-TRAY
Sharp code: RH-IXD378WJZZQ
 Enable 100/120 Hz panels in any design.
 LCD motion blur reduction.
 Film judder removal.
 Enable 3D polarized/Shutter glass display.
 Frame reate conversión 24 to 50/60 or 100/120, 50/60 to 100/120.
 Other frame rate available (48,72,96,…).
 Automatic cadence detection (3/2,2/2,…).
 Spread spectrum support for DDR2 and LVDS with integrated 3D formatter.
 Black bar detection.
 Low video latency, game mode support.
 True internal 11-bit processing on 4:4:4 color space.
 Overdrive.
 LED local dimming processor direct and edge with pixel compensation.
 Dual LVDS input, quad LVDS output.
 Single HS LVDS input and Dual HS LVDS output.
 VbyOneHS output.
 16-bit DDR2/3-1066Mbit interface.
 Power
o 1.2V core voltaje, 1.8V or 1.5V Memory, 2.5/3.3V I/O
 Packaging
o
BGA package 23x23 mm Plastic Ball Grid Array package
o 328 balls
o
Fully-Green.
• IC 3501 & IC 3502 : DDR3 SDRAM
Part number: K4B2G1646C-HCH9
Sharp code: RH-IX242WJQZQZ
http://www.samsung.com/global/system/business/semiconductor/product/2009/1/13/925951ds_k4b2gxx46b_rev10.pdf
The 2Gb DDR3 SDRAM B-die is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for
general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS,
Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset. All of the control
and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are
synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to
convey row, column, and bank address information in a RAS/CAS multiplexing style.
Features:
 JEDEC standard 1.5V ± 0.075V Power Supply.

VDDQ = 1.5V ± 0.075V.
 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK
for 1600Mb/sec/pin.
 8 Banks.
 Posted CAS.
 Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10.
 Programmable Additive Latency: 0, CL-2 or CL-1 clock.
 Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600).
 8-bit pre-fetch.
 Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does
not allow seamless read or write [either On the fly using A12 or MRS].
 Bi-directional Differential Data-Strobe.
 Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%).
 On Die Termination using ODT pin.
 Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C.
 Asynchronous Reset.
 Package : 96 balls FBGA - x16.
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