Sharp DV-SL800W, Руководство по обслуживанию

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DV-SL800W
57
Symbol Pin NO I/O Description
M_CS0_B/GPIO 100 IO
SDRAM chip select 0, or GPIO[24]
M_BAO
101 IO
SDRAM bank select address [0]
M_DD[15]
102 IO
SDRAM data bus [15]
M_DD[14]
103 IO
SDRAM data bus [14]
M_DD[13]
104 IO
SDRAM data bus [13]
VDD_K2
105 S
Kernel logic power supply#2
M_DD[12]
106 IO
SDRAM data bus [12]
M_DD[11]
107 IO
SDRAM data bus [11]
M_DD[10]
108 IO
SDRAM data bus [10]
M_DD[9]
109 IO
SDRAM data bus [9]
M_DD[8]
110 IO
SDRAM data bus [8]
M__A[11]/GPIO 111 IO
SDRAM address bus [11] or GPIO [25]
VDD_03
112 S
l/O power supply #3
M_CLKO
113 O
SDRAM clock output
VSS_03/VSS_K3
114 S
Kernel logic/l/O power shared ground supply #3
M_CKE/GPIO 115 IO
SDRAM clock enable, or gpio[26]
M_A[9]
116 lO
SDRAM address bus [9]
M_A[8]
117 lO
SDRAM address bus [8]
M_A[7]
118 lO
SDRAM address bus [7]
M_A[6]
119 l/O
SDRAM address bus [6]
M_A[5]
120 l/O
SDRAM address bus [5]
VDD_K3
121 S
Kernel logic power supply #3
M_A[4]
122 I/O
SDRAM address bus [4]
M_DQM1/GPIO
123 I/O
SDRAM data input/output mask for M_DD[15:8] or GPIOA[27]
M_DQM0/GPIO 124 I/O
SDRAM data input/output mask for M_DD[7:0] or GPIOA[28]
M_BA1/GPIO 125 I/O
SDRAM bank select address [1] or GPIOA[29]
Priority selection Function Dir
sft_cfg0[0]=1'b1
SDRAM chip select
(default)
O
sft_cfg8[9]=1'b1 DAC_DATA_D[2] I
(other) GPIO[24] I/O
Priority selection Function Dir
sft_cfg1[4]=1'b1
SDRAM address bus
M_A[11] (default)
O
sft_cfg8[9]=1'b1
DAC_DATA_C[2] I
(other)
GPIO[25] I/O
Priority selection Function Dir
sft_cfg0[1]=1'b1
DRAM clock enable
(default)
O
sft_cfg8[9]=1'b1
DAC_DATA_C[1] I
(other)
GPIO[26] I/O
Priority selection Function Dir
sft_cfg0[2] SDRAM data input/output I/O
mask for M_DD[7,8]
(default)
sft_cfg8[8]=1'b1 ADC_MONO _D_R[5] O
sft_cfg8[9]=1'b1 DAC_DATA_B[3] I
(other) GPIO[28] I/O
Priority selection Function Dir
sft_cfg0[6]=1'b1 SDRAM bank select
I/O
address [1] (default)
sft_cfg8[8]=1'b1 ADC_MONO _D_R[6]
O
sft_cfg8[9]=1'b1 DAC_DATA_B[2]
I
(other) GPIO[29]
I/O