DV-SL800W
68
IC106 & IC107, COMS DRAM 143MHZ 16MB
Functional Block Diagram:
512Kx16
Bank 0
Column Addr
Latch & Counter
512Kx16
Bank 1
Address
Register
Burst Length
Counter
Refresh
Interval Timer
Refresh
counter
Address[0:10]
CLK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CKE
BA(A11)
CS
RAS
CAS
WE
UDQM
LDQM
Mode Register
Test Mode
I/O Control
Overflow
State
Machine
Column Decoder
Column Decoder
Precharge
Column Active
Row Active
Self Refresh Counter
Sense AMP & I/O gates
Sense AMP & I/O gates
Row
Addr
.Latch/Predecoder
Data
Input/Output
Buf
fers
Row
Decoder
Ref.
Addr[0:1
1]
Auto/Self
Refresh
Row
Addr
.Latch/Predecoder
Содержание DV-SL800W
Страница 11: ...DV SL800W 11 MEMO ...
Страница 31: ...DV SL800W 31 MEMO ...
Страница 82: ...DV SL800W 7 MEMO ...
Страница 83: ...DV SL800W 8 MEMO ...