X86
UDOO X86 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by M.B. Copyright © 2017 SECO S.r.l.
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4.3.4.5
PCI Express configuration submenu
4.3.4.5.1
PCI Express Root Port #x configuration submenus
Menu Item
Options
Description
PCI Express Port 1 (M.2 Slot CN20)
PCI Express Port 2 (Internal LAN)
PCI Express Port 3 (M.2 Slot CN19)
See submenu
Menu Item
Options
Description
PCI Express Root Port #1
PCI Express Root Port #2
PCI Express Root Port #3
Disabled / Enabled
Enable or Disable single PCI Express Root Port #x.
PCI Express Root Port #2 is internally connected to the Gigabit Ethernet Controller. Disabling
this port will result in disabling the corresponding Ethernet interface.
When a single Root Port is disabled all the following menu items are disabled
ASPM
Disabled / Auto / L0s / L1 / L0s
& L1
Manages PCI Express L0s and L1 power states, for OSs able to handle Active State Power
Management (ASPM).
URR
Disabled / Enabled
PCI Express Unsupported Request Reporting Enable or Disable
FER
Disabled / Enabled
PCI Express Fatal Error Reporting Enable or Disable
NFER
Disabled / Enabled
PCI Express Non-Fatal Error Reporting Enable or Disable
CER
Disabled / Enabled
PCI Express Correctable Error Reporting Enable or Disable
SEFE
Disabled / Enabled
PCI Express System Error on Fatal Error Enable or Disable
SENFE
Disabled / Enabled
PCI Express System Error on Non-Fatal Error Enable or Disable
SECE
Disabled / Enabled
PCI Express System Error on Correctable Error Enable or Disable
PME SCI
Disabled / Enabled
Enables or disables use of ACPI SCI (System Control interrupt) on a PME (Power
Management Event).
Ext Sync
Disabled / Enabled
PCI Express Ext Sync Enable or Disable
PCI Express Speed
Auto / Gen1 / Gen2
Set PCI-e ports link speed/capability.
Transmitter Half Swing
Disabled / Enabled
Enable or Disable Transmitter Half Swing
L1 Substates
Disabled / L1.1 & L1.2 / L1.1 /
L1.2
PCI Express L1 Substates settings.
