CCOMe-C79
CCOMe-C79 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by E.S. Copyright © 2021 SECO S.p.A.
36
CB_RESET# using a Ultra High Speed CMOS
buffer. Active low signal, +3.3V_ALW electrical level
with a 100k
pull down resistor.
Not Connected
RSVD
B12
A12
GND
Power Ground
Power Ground
GND
B13
A13
PCIEx4_1_CLK_P
PCI-e reference clock lane +, derived by
PCIE using a Clock Buffer
PCI-e Transmitter lane 0+
P
B14
A14
PCIEx4_1_CLK_N
PCI-e reference clock lane +, derived by
PCIE_CK_REF- using a Clock Buffer
PCI-e Transmitter lane 0-
PCIE_TX0-
B15
A15
GND
Power Ground
Power Ground
GND
B16
A16
P
PCI-e Receiver lane 0+
Hot Plug presence detect. Input Signal from add in
card used to enable the reference clock of this slot.
Active low signal, +3.3V_RUN electrical level with a
10k
PRSNT2#
B17
A17
PCIE_RX0-
PCI-e Receiver lane 0-
Power Ground
GND
B18
A18
GND
Power Ground
PCI-e Transmitter lane 1+
P
B19
A19
RSVD
Not Connected
PCI-e Transmitter lane 1-
PCIE_TX1-
B20
A20
GND
Power Ground
Power Ground
GND
B21
A21
P
PCI-e Receiver lane 1+
Power Ground
GND
B22
A22
PCIE_RX1-
PCI-e Receiver lane 1-
PCI-e Transmitter lane 2+
P
B23
A23
GND
Power Ground
PCI-e Transmitter lane 2-
PCIE_TX2-
B24
A24
GND
Power Ground
Power Ground
GND
B25
A25
P
PCI-e Receiver lane 2+
Power Ground
GND
B26
A26
PCIE_RX2-
PCI-e Receiver lane 2-
PCI-e Transmitter lane 3+. Signal available to this
slot by setting jumper JP6 in 2-3 position.
P
B27
A27
GND
Power Ground
PCI-e Transmitter lane 3-. Signal available to this
slot by setting jumper JP6 in 2-3 position.
PCIE_TX3-
B28
A28
GND
Power Ground
Power Ground
GND
B29
A29
P
PCI-e Receiver lane 3+. Signal available to this slot
by setting jumper JP6 in 2-3 position.
Not Connected
RSVD
B30
A30
PCIE_RX3-
PCI-e Receiver lane 3-. Signal available to this slot
by setting jumper JP6 in 2-3 position.
Hot Plug presence detect. Input Signal from add in
card used to enable the reference clock of this slot.
Active low signal, +3.3V_RUN electrical level with a
PRSNT2#
B31
A31
GND
Power Ground
