4.193
Date Code 20170814
Instruction Manual
SEL-700G Relay
Protection and Logic Functions
Logic Settings (SET L Command)
Figure 4.132
Typical Feeder Close CL Logic (SEL-700GW)
Unlatch Close Logic
Each of the two close logic equations has an associated unlatch close
SEL
OGIC
control equation. Once the CLOSE bit is asserted, it is sealed-in
until any of the following conditions are true:
➤
Unlatch Close SEL
OGIC
control equation setting ULCLX (or
ULCLY) asserts to logical 1.
➤
Relay Word bit 52AX (or 52AY) asserts to logical 1.
➤
Close failure Relay Word bit asserts to logical 1.
Close Failure Logic
Each of the two close logic equations includes a close failure detection with an
associated delay setting CFDX and CFDY. Set the close failure delay (setting
CFD) equal to the highest breaker close time plus a safety margin. If the
breaker fails to close, the Relay Word CFX (or CFY) asserts for 1/4 cycle. Use
the CF bit as necessary.
Logic Settings (SET L Command)
The settings associated with latches, timers, counters, math variables, and
output contacts are listed below.
SEL
OGIC
Enables
Table 4.54 shows the enable settings for latch bits (ELAT), SEL
OGIC
control
equations (including timers) (ESV), Counters (ESC), and math variable
equations (EMV). This helps limit the number of settings that you need to
make. For example, if you need six timers, only enable six timers.
(a) CLX Logic
(b) CLY Logic
SV03T
LT02
CCX
CLX
INxxx
CLY
CCY
SV03T
LT02
INyyy
Table 4.54
Enable Settings
Setting Prompt
Setting Range
Default Setting
SEL
OGIC
Latches
N, 1–32
ELAT := 6
SV/Timers
N, 1–32
ESV := 12
SEL
OGIC
Counters
N, 1–32
ESC := N
Math Variables
N, 1–32
EMV := N
Содержание SEL-700G Series
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