Sanyo FISHER DVD-1500 AU, Руководство по обслуживанию

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IC BLOCK DIAGRAM & DESCRIPTION
No. Name I/O DESCRIPTION No. Name I/O DESCRIPTION
1 VSS -
Digital ground
51
2VREF - Analogue reference power
2 BCK O Bit clock(1.4122MHz) output 52
SEL O APC circuit on/off signal output
3 AOUT O Audio data output 53
FLGA O External flag of internal signal monitor output
4 DOUT O Digital output 54
FLGB O External flag of internal signal monitor output
5 MBOV O Buffer memory over signal output 55
FLGC O External flag of internal signal monitor output
6 IPF O Correction flag output 56
FKGD O External flag of internal signal monitor output
7 SBOK O CRCC judgement result of subcode "Q" data output 57
VDD - Digital pulse power source
8 CLCK I/O Clock output for subcode "P"~"W" data read 58
VSS - Digital ground
9 VDD -
Digital power plus source.
59
IOO I/O General purpose I/O port
10 VSS -
Digital ground.
60
IO1 I/O General purpose I/O port
11 DATA O Subcode "P"~"W" data output. 61
IO2 I/O General purpose I/O port
12 SFSY O Frame synchronism signal output by play. 62
IO3 I/O General purpose I/O port
13 SBSY O Subcode block synchronism output 63
/DMOUT I Mode setting for IO0,1,2,3
14 SPCK O Clock output for process status signal read 64
/CKSE I X'tal select
15 SPDA O Processor status signal output. 65
/DACT I Test
16 COFS O Frame clock(7.35kHz) output by amendment 66
TESIN I Test input
17 MONIT O LSI internal signal monitor 67
TESTIO1 I Test input/output
18 VDD -
Digital power plus source.
68
VSS - Digital ground
19 TESIO0 I
Test input/output
69
PXI I "DSP" clock oscillator input
20 P2VRREF -
2V REF by PLL only
70
PXO O "DSP" clock oscillator output
21 SPDO O VCO sensor frequency shift 71
VDD - Digital pulse power source
22 PDOS O output of phase error between EFM signal and PLC signal 72
XVSS - Ground for system clock oscillator
23 PDO O output of phase error between EFM signal and PLCK signal 73
XI I System clock oscillator input
24 TMAXS O TMAX detection result output 74
XO O System clock oscillator output
25 TMAXS O TMAX detection result output 75
XVDD - System clock oscillator pulse power source
26 LPFN I
Inversion of low pass filter amplifier input
76
DVDD - power source for D/A converter
27 LPFO O Low pass filter amplifier output 77
RO O "R" channel data output
28 PVREF -
Dedication of PLL VREF
78
DVSS - D/A converter analogue Ground
29 VCOREF I
VCO sensor frequency reference level
79
DVR - D/A converter Reference power source
30 VCOF O VCO filter 80
LO O "L" channel data output
31 AVSS -
Analogue ground
81
DVDD - D/A converter power source
32 SLCO O Data slice level generation "DAC" output 82
TEST1 I Test port
33 RFI I
RF signal input
83
TEST2 I Test port
34 AVDD -
Analogue power source
84
TEST3 I Test port
35 RFCT I
RFRP signal sensor level input
85
BUSO I/O Data input for micon interface
36 RFZI I
RFRP zero cross input
86
BUS1 I/O Data input for micon interface
37 RFRP I
Ripple
87
BUS2 I/O Data input for micon interface
38 FEI I
Focus error signal input
88
BUS3 I/O Data input for micon interface
39 SBAD I
Subbeam additional signal input
89
VDD - Digital power source
40 TSIN I
Test input
90
VSS - Digital ground
41 TEI I
Tracking error input
91
BUCK I Clock input for micon interface
42 TEZI I
Tracking error zero cross input
92
/CCE I Chip enable signal input for micon interface
43 FOO O Focus equaliser output 93
TEST4 I Test port
44 TRO O Tracking equaliser output 94
/TSMOD I Local test mode selector
45 VREF -
Analogue reference power
95
/RST I Reset signal input
46 RFGC O RF magnitude regulation control output 96
TEST0 I Test port
47 TEBC O Tracking Blanca control signal output 97
/HSO O Play speed mode flag output
48 FMO O Field equaliser output 98
/UHSO O Play speed mode flag output
49 FVO O Speed error signal or Field search "EQ" output 99
EMPH O Subcode "Q" data emphasis flag output
50 DMO O Disc equaliser output 100
LRCK O Channel clock(44.1kHz) output
IC701 TC9461F(DIGITAL SERVO SIGNAL PROCESSOR)
IC904 MC74HC00AF(QUAD 2-INPUT NAND)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
GND
IC903 MC74HC175DR(QUAD D FLIP-FLOP)
1
2
3
4
5
6
7
8
VCC
Q3
Q3
D3
D2
Q2
Q2
CLOCK
16
15
14
13
12
11
10
9
Inputs Output
Reset
L
H
H
H
D
X
H
L
X
Q
L
H
L
Q
H
L
H
Clock
X
L No Change