- 70 -
IC BLOCK DIAGRAM & DESCRIPTION
IC002 ADV7172KST
(PAL and NTSC square pixel operation)
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
CGMS & WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
4:2:2 TO
4:4:4
INTER-
POLATOR
YCrCb
TO
YUV
MATRIX
ADD
SYNC
INTER-
POLATOR
INTER-
POLATOR
ADD
BURST
PROGRAMMABLE
LUMINANCE
FILTER
PROGRAMMABLE
CHROMINANCE
FILTER
VIDEO TIMING
GENERATOR
I C MPU PORT
2
REAL-TIME
CONTROL
CIRCUIT
SIN/COS
DDS BLOCK
VOLTAGE
REFERENCE
CIRCUIT
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
YUV TO
RBG
MATRIX
M
U
L
T
I
P
L
E
X
E
R
U
U
10
10
10
10
10
10
10
10
10
10
10
10
V
V
8
8
9
8
8
9
8
8
8
8
8
8
44
23
24
18
35
32
31
26
27
37
36
22
16
15
17
34
33
25
Y
1,11,20,28,30
4-2
43-38
14-12
9-5
10,19,29,43
Vss
CLOCK
DATA
P7-P0
P15-P8
RESET
HSYNC
FIELD/VSYNC
BLANK
CLOCK
SCLOCK
SDATA
ALSB
SCRESET/RTC
GND
COMP
DAC A(PIN 32)
GAC B(PIN 31)
DAC C(PIN 26)
DAC D(PIN 27)
R
SET
V
REF
TTXREQ
TTX
IC003 BA7660FS(3 CHANNEL 75 OHM DRIVER)
1
2
3
4
5
6
7
8
MUTE
INA
GND
INB
GND
N.C.
INC
GND
VCC
OUTA1
OUTA2
OUTB1
OUTB2
N.C.
OUTC1
OUTC2
16
15
14
13
12
11
10
9
6dB
75
Ω
6dB
75
Ω
6dB
75
Ω
IC015 MC74H174AD(HEX D-TYPE FLIP-FLOP)
1
2
3
4
5
6
7
8
RESET
Q0
D0
D1
Q1
D2
Q2
GND
VCC
Q5
D5
D4
Q4
D3
Q3
CLOCK
16
15
14
13
12
11
10
9
Inputs
Output
Reset
L
H
H
H
H
D
X
H
L
X
X
Q
L
H
L
No Change
No Chenge
Clock
X
L
IC101 24LC16B/P (16K EEPROM)
Name
Function
V
SS
SDA
SCL
WP
V
CC
A0,A1,A2
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
4
3
2
1
5
6
7
8
SDA
SCL
WP
V
CC
V
SS
A2
A1
A0
24LC
16B
IC115 PCM1723(D/A CONVERTER)
No.
Name
I/O DESCRIPTION
1
XT1
-
27 MHz x'tal oscillate input or external oscillator
2
SCKO
O System clock output
3
VCP
-
PLL power source
4
NC
-
N.C
5
MCKO
O Master clock buffer output
6
M L
I
Software control latch
7
MC
I
Software control clock
8
MD
I
Software control data
9
RSTB
I
Reset
10
ZERO
O Zero data flag output
11
VOUTR
O Rch. Analogue power output
12
GNDA
-
Analogue ground
13
VCA
-
Analogue power 5V
14
VOUTL
O Lch. Analogue power output
15
CAP
-
Output amplifier common
16
BCKIN
I
Bit clock input for data
17
DIN
I
Data input
18
LRCIN
I
Basic sampling clock input
19
NC
-
N.C
20
RSV
-
N.C
21
VDD
-
Digital power source 5V
22
GNDD
-
Digital ground
23
GNDP
-
PLL ground
24
XTO
-
Crystal oscillator
IC117 T2316162A-45J(1024 x 16 DRAM)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
SS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
OE
CASL
CASH
V
SS
V
CC
DQ0
DQ1
DQ2
DQ4
DQ5
DQ6
DQ7
DQ3
NC
NC
WE
V
CC
15
16
17
18
19
20
21
28
27
26
25
24
23
22
NC
A7
A8
A9
A6
A5
A4
V
SS
RAS
A0
NC
NC
A1
A2
A3
V
CC
SYM.
TYPE
DESCRIPTION
Address Input
Row Address Strobe
Column Address Stlobe /Upper Byte Control
Column Address Stlobe /Lower Byte Control
Write Enable
Output Enable
Data Input /Output
Power, 5V
Ground
No Connec
A0~A9
RAS
CASH
CASL
WE
OE
DQ0~DQ15
V
CC
V
SS
NC
Input
Input
Input
Input
Input
Input
Input/Output
Supply
Ground
-
Содержание FISHER DVD-1500 AU
Страница 42: ... 55 MPEG P W BOARD CHECK WAVEFORM 1 2 3 4 5 6 Indicate each signaling in schematic diagram of MPEG P 58 ...
Страница 44: ... 57 MPEG P W BOARD CHECK WAVEFORM 8 9 10 11 12 ...
Страница 65: ... 82 WIRING DIAGRAM DVD A SIDE ...
Страница 66: ... 83 WIRING DIAGRAM DVD B SIDE ...
Страница 67: ... 86 WIRING DIAGRAM MPEG A SIDE for AU ...
Страница 68: ... 87 WIRING DIAGRAM MPEG B SIDE for AU ...
Страница 69: ... 90 WIRING DIAGRAM MPEG A SIDE for US ...
Страница 70: ... 91 WIRING DIAGRAM MPEG B SIDE for US ...
Страница 72: ... 97 AMP for AU WIRING DIAGRAM AMP AMP for US ...
Страница 74: ...SANYO Technosound Co Ltd Osaka Japan Jun 00 2550 BB Printed in Japan ...