- 73 -
IC BLOCK DIAGRAM & DESCRIPTION
IC501 TA1254AF(RF SIGNAL PROCESSER)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCKF
VccP
LVL
TEO
FEO
DFTN
VssS
RPZ
RPO
RPB
RPP
RFO
NC
NC
VccR
DPDB
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P2FN
P2FP
GNDS
P2DI
P2CI
P2BI
P2AI
LDP2
GNDR
P1AI
P1BI
P1CI
P1DI
LDP1
P1FP
P1FN
TEB
FEB
PSC
Vcc2
NC
EQD
GND2
RFDC
RF
A
EQB
EQF
MDI1
LDO1
P1TN
P1TP
NC
VRCK
SCD
SCL
SCB
DPD2
DPD1
DPBD
DP
A
C
Vdd
VrD
VrA
MDI2
LDO2
P2TN
P2TP
GND
F-gain
Adjustment
F-gain
Adjustment
T-gain
Adjustment
R-gain
Adjustment
TE-gain
Adjustment
FTE-gain
Adjustment
Level
Detection
BUS
Time
Constant
Adjustment
APC2
APC1
3BTE
Generation
DPDTE
Generation
FE
Generation
RF Ripple
Generation
EQ
sel-DPD
sel-LVL
sel-FE
sel-PD
sel-RF
sel-TE
mode-IC
mode-TE
PIN
NO.
-
I
I
O
I
O
O
I
-
-
-
-
I
I
I
I
-
-
O
O
O
I
-
O
O
O
O
O
-
-
-
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I
I
I
-
-
I
-
-
O
I
I
I
O
I
I
-
I
I
I
I
I
I
I
-
I
I
I
I
I
-
I
I
VrD
VrD
-
-
VrD
VrD
-
-
2.2[V]
VrD
VrD
-
-
VrA
VrA
-
VrA
VrA
-
VrA
VrA
VrA
VrA
-
-
VrA
VrA
VrA
VrA
-
VrA
VrA
-
VrA
VrA
-
-
2.1[V]
-
-
-
-
-
2.2[V]
2.2[V]
2.2[V]
2.3[B]
-
-
VrD
VrD
VrD
-
-
VrD
VrD
-
-
2.3[V]
-
-
-
VrD
GND
TE+(CD)
TE-(CD)
DRIVE
MONITOR
ANALOG VREF
DIGITAL VREF
POWER SOURCE
DPD AC COMBINATOIN CAPACITY 1
DPD AC COMBINATION CAPACITY 2
DPD INTEGRAL CAPACITY 1
DPD INTEGRAL CAPACITY 2
CONTROL LINE(BIT CLOCK)
CONTROL LINE(LATCH SIGNAL)
CONTROL LINE(SERISL DATA)
REFERENCE CLOCK
TIME CONSTANT
POWER SOURCE
SERVO ADDITION
TE
FE
DPD DEFECT
POWER SOURCE(SERVO)
RF RIPPLE CENTER VOLTAGE
RF RIPPLE
RF RIPPLE BOTTOM
RF RIPPLE PEAK
EQUALIZING RF
NO CONNECTION
NO CONNECTION
POWER SOURCE(RF)
PIT DEPTH ADJ.
TE BALANCE
FE BALANCE
VRCK DIVIDING
POWER SOURCE
NO CONNECTION
GROUP DELAY CORRECTION
GND
DC FADE BACK
RF ALL ADDITION
BOOST ADJ.
FREQUENCY CONTROL
MONITOR
DRIVE
TE-
TE+
NO CONNECTION
FE-
FE+
APC POLARITY 1
D(DVD)
C(DVD)
B(DVD)
A(DVD)
GND
APC POLARITY 2
A(CD)
B(CD)
C(CD)
D(CD)
GND(SERVO)
FE+(CD)X
FE-(CD)
GND
P2TP
P2TN
LDO2
MDI2
VrA
VrD
Vdd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
VRCK
VCKF
VccP
LVL
TEO
FEO
DFTN
VccS
RPZ
RPO
RPB
RPP
RFO
NC
NC
VccR
DPDB
TEB
FEB
PSC
Vcc2
NC
EQD
GND2
RFDC
RFA
EQB
EQF
MDI1
LDO1
P1TN
P1TP
NC
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
SYM.
I/O
FUNCTION
TERM.
V
PIN
NO.
SYM.
I/O
FUNCTION
TERM.
V
IC701 TC9461F(DIGITAL SERVO SIGNAL PROCESSOR)
DVDD
RD
DVSS
DVR
LO
DVDD
TEST1
TEST2
TEST3
BUS0
BUS1
BUS2
BUS3
VDD
VSS
BUCK
/CCE
TEST4
/TSMOD
/RST
TEST0
/HSO
/UHSO
EMPH
LRCK
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DMO
FVO
FMO
TEBC
RFGC
VREF
TRO
FDO
TEZI
TEI
TSIN
SBAD
FEI
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RFRP
RFZI
RFCT
AVDD
RFI
SLCO
AVSS
VCOF
VCOREF
PVREF
LPFO
LPFN
XVDD
XO
XI
XVSS
VDD
PXO
PXI
VSS
TESIO1
TESIN
/D
A
C
T
/CKSE
/DMOUT
IO3
IO2
IO1
IOO
VSS
VDD
FLGD
FLGC
FLGB
FLGA
SEL
2VREF
VSS
BCK
A
OUT
DOUT
MBO
V
IPF
SBOK
CLCK
VDD
VSS
D
ATA
SFSY
SBSY
SPCK
SPD
A
COFS
MONIT
VDD
TESIO0
P2VREF
SPD0
PDOS
PD0
TMAXS
TMAX
+
-
+
-
+
-
+
-
LPF
1 BIT
DAC
CLOCK
GENERATOR
SERVO
CONTROL
PWM
D/A
ROM
A/D
RAM
DIGITAL
EQUALIZER
SDDRESS
CIRCUIT
CLV SERVO
MICRO-
COMPUTER
INTERFACE
16k RAM
CORRECT
CIRCUIT
DIGITAL OUT
AUDIO OUTPUT
CIRCUIT
SUB CODE
DEMOJULATION
STATUS
PLL TMAX
VCO
PWM
DATA
SLICER
SYNCHRONIZING
SIGNAL PROTECT
EFM DEMOJULATION
AUTOMATIC
CONTROL
CIRCUIT
IC501 TA1254AF(RF SIGNAL PROCESSER)
Содержание FISHER DVD-1500 AU
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