8-69
R530/R730
8. Block Diagram and Schematic
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
1 OF
5
VT
T
HOST DATA BUS
VTTLF
NC
HOST CONTROL
HOST ADDRESS BUS
VCC CORE
CF
G
Enabled (def.
)
CHECK
DRA
W
C
iTPM Host Interface Enable
Simultaneousl
y
MODULE CODE
DMI Lane Reversal
PROPRIETARY INFORMATION THAT IS
CFG(7)
4
DMIx4 (def.)
CFG(19)
PEG Reversal (def.)
iTPM option
ELECTRONICS
DMIx2
RE
V
Low
2
D
4
DMI Lane Normal (def.)
1608
TITLE
SDVO or PCIE X1
EXCEPT AS AUTHORIZED BY SAMSUNG
.
A
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHER
S
Dynamic OD
T
Only(def.
)
3
Current Settin
g
ME Crypto confidentiality (def.)
2
D
Normal
CFG(5)
C
CFG#
P
A
G
E
DAT
E
THIS DOCUMENT CONTAINS CONFIDENTIA
L
DEV. STEP
B
SDVO and PCIE X1
3
13
50
Bremen-UL
MCH_CANTIGA_GM_DDR
2
CANTIGA (1/5)
D:/users/mobile29/mentor/Bremen-UL/Bremen-UL_Et
c
Hig
h
(def. : default Option)
SAMSUN
G
PCIE Loop Back Enable
CFG(20
)
*POCAFEB-12 Only (Remove in MP Model)
APPROVAL
CFG(16)
1
B
ME Crypto no confidentialit
y
Dynamic ODT Disabled
LAST EDIT
OF
SAMSUNG ELECTRONICS CO’S PROPERTY.
CFG(10)
A
CFG(9)
1
SAMSUNG PROPRIETAR
Y
iTPM Host Interface Disable (def.)
PCIE Loop Back Disable(def
)
PART NO
.
CFG(6)
14
33
TW.Kim
HJ.Kim
SJ.Park
undefined
9/23/2008
ADV2nd
1.0
October 05, 2009 20:00:56 PM
BA41-xxxxxA
6.3V
C
65
6
10000nF-X5
R
23
56
19
53
19
60
44
50
11
0
7
10000nF-X5R
C
64
8
6.3V
32
31
4
C664
16V
16V
C103
470nF
470nF
14
16V
C608
470nF
12
41
nostuf
f
9
EC504
220uF
2.5V
8
52
23
P1.05V
35
36
48
15
45
3
6
58
59
17
17
7
8
1% 10
0
R
58
8
32
10V
C
60
9
100nF
2.5V
220uF EC503
nostuf
f
1%
24.9
R72
20
3
63
nostuf
f
4
26
10000nF-X5
R
C661
6.3V
22
1000nF-X5
R
C
65
3
6.3V
22
VTT_6 T5
VTT_7 T6
VTT_8 T7
VTT_9 T8
P1.05V
13
VTT_19 U6
VTT_2 T11
VTT_20 U7
VTT_21 U8
VTT_22 U9
V1
VTT_23 V2
VTT_24 V3
VTT_25
VTT_3 T12
VTT_4 T13
VTT_5 T2
L1
VTT_1 T10
VTT_10 T9
VTT_11 U1
VTT_12 U10
VTT_13 U11
VTT_14 U12
VTT_15 U13
VTT_16 U2
VTT_17 U3
VTT_18 U5
Y29 VCC_NCTF_42
Y30 VCC_NCTF_43
Y32 VCC_NCTF_44
AC29 VCC_NCTF_5
AC30 VCC_NCTF_6
AC32 VCC_NCTF_7
AE29 VCC_NCTF_8
AE30 VCC_NCTF_9
VTTLF_1
A8
VTTLF_2
AB
2
VTTLF_3
VCC_NCTF_32
AM30 VCC_NCTF_33
AM32 VCC_NCTF_34
U30 VCC_NCTF_35
U32 VCC_NCTF_36
V29 VCC_NCTF_37
V30 VCC_NCTF_38
W29 VCC_NCTF_39
AB30 VCC_NCTF_4
W30 VCC_NCTF_40
W32 VCC_NCTF_41
VCC_NCTF_22
AK26 VCC_NCTF_23
AK28 VCC_NCTF_24
AK29 VCC_NCTF_25
AK30 VCC_NCTF_26
AK32 VCC_NCTF_27
AL26 VCC_NCTF_28
AL28 VCC_NCTF_29
AA32 VCC_NCTF_3
AL29 VCC_NCTF_30
AL30 VCC_NCTF_31
AL32
AG30 VCC_NCTF_13
AG32 VCC_NCTF_14
AH29 VCC_NCTF_15
AH30 VCC_NCTF_16
AH32 VCC_NCTF_17
AJ29 VCC_NCTF_18
AJ32 VCC_NCTF_19
AA30 VCC_NCTF_2
AK23 VCC_NCTF_20
AK24 VCC_NCTF_21
AK25
VCC_35
VCC_4 AB34
VCC_5 AC26
VCC_6 AC28
VCC_7 AC33
VCC_8 AC34
VCC_9 AE26
AA29 VCC_NCTF_1
AE32 VCC_NCTF_10
AF30 VCC_NCTF_11
AG29 VCC_NCTF_12
VCC_25 AK33
VCC_26 AM33
VCC_27 T32
VCC_28 U33
VCC_29
VCC_3 AA34
U34
VCC_30 V33
VCC_31 V34
VCC_32 W33
VCC_33 Y33
VCC_34 Y34
AG25
VCC_16 AG26
VCC_17 AG33
VCC_18 AG34
VCC_19
VCC_2 AA33
AH23
VCC_20 AH25
VCC_21 AH28
VCC_22 AJ23
VCC_23 AJ26
VCC_24 AJ33
H_RS#_1
C8
H_RS#_2
H_SWING
C5
C9
H_TRDY
#
VCC_1 AA28
VCC_10 AE33
VCC_11 AF23
VCC_12 AF25
VCC_13 AF28
AF33
VCC_14 AG24
VCC_15
B1
1
H9
H_HIT#
E1
2
H_HITM
#
H1
1
H_LOCK#
H_RCOMP
E3
B1
5
H_REQ#_0
K13
H_REQ#_1
F13
H_REQ#_2
B1
3
H_REQ#_3
B14
H_REQ#_4
B6
H_RS#_0
F12
J11
H_DPWR#
F9
H_DRDY#
L10
H_DSTBN#_0
M7
H_DSTBN#_1
AA
5
H_DSTBN#_2
AE
6
H_DSTBN#_3
L9
H_DSTBP#_0
M8
H_DSTBP#_1
AA
6
H_DSTBP#_2
AE
5
H_DSTBP#_3
H_DVRE
F
H_D#_62
AD
6
H_D#_63
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
B1
0
H_DBSY
#
E9
H_DEFER#
J8
H_DINV#_0
L3
H_DINV#_1
Y13
H_DINV#_2
Y1
H_DINV#_3
H_D#_52
AD
3
H_D#_53
AD
7
H_D#_54
A
E
14
H_D#_55
AF
3
H_D#_56
AC
1
H_D#_57
AE
3
H_D#_58
AC
3
H_D#_59
H2
H_D#_6
AE11
H_D#_60
AE
8
H_D#_61
AG
2
AA
9
H_D#_43
AA11
H_D#_44
A
D
11
H_D#_45
A
D
10
H_D#_46
A
D
13
H_D#_47
AE12
H_D#_48
AE
9
H_D#_49
H6
H_D#_5
AA
2
H_D#_50
AD
8
H_D#_51
AA
3
H_D#_3
3
Y6
H_D#_3
4
Y1
0
H_D#_3
5
Y1
2
H_D#_3
6
Y1
4
H_D#_3
7
Y7
H_D#_3
8
W2
H_D#_3
9
G2
H_D#_4
AA8
H_D#_4
0
Y9
H_D#_4
1
AA13
H_D#_4
2
H_D#_2
3
R1
H_D#_2
4
N5
H_D#_2
5
N6
H_D#_2
6
P1
3
H_D#_2
7
N8
H_D#_2
8
L7
H_D#_2
9
E6
H_D#_3
N10
H_D#_3
0
M3
H_D#_3
1
Y3
H_D#_3
2
AD1
4
N12
H_D#_1
4
J6
H_D#_1
5
P2
H_D#_1
6
L2
H_D#_1
7
R2
H_D#_1
8
N9
H_D#_1
9
F8
H_D#_2
L6
H_D#_2
0
M5
H_D#_2
1
J3
H_D#_2
2
N2
H_BNR
#
F1
1
H_BPRI
#
G12
H_BREQ#
C1
2
H_CPURST#
E1
1
H_CPUSLP
#
F2
H_D#_0
G8
H_D#_1
M9
H_D#_1
0
M1
1
H_D#_1
1
J1
H_D#_1
2
J2
H_D#_1
3
H_A#_3
5
C15
H_A#_
4
F1
6
H_A#_
5
H13
H_A#_
6
C18
H_A#_
7
M1
6
H_A#_
8
J1
3
H_A#_
9
H12
H_ADS#
B1
6
H_ADSTB#_
0
G17
H_ADSTB#_
1
H_AVREF
A11
A9
L1
6
H_A#_2
6
C21
H_A#_27
J1
7
H_A#_28
H20
H_A#_2
9
A1
4
H_A#_
3
B1
8
H_A#_30
K1
7
H_A#_31
B2
0
H_A#_3
2
F2
1
H_A#_33
K2
1
H_A#_3
4
L2
0
H_A#_15
F1
7
H_A#_1
6
G20
H_A#_1
7
B1
9
H_A#_1
8
J1
6
H_A#_19
E2
0
H_A#_2
0
H16
H_A#_2
1
J2
0
H_A#_22
L1
7
H_A#_2
3
A1
7
H_A#_2
4
B1
7
H_A#_2
5
CFG_6
M24 CFG_7
E21 CFG_8
C23 CFG_9
HPLL_CLK
AH
7
AH
6
HPLL_CLK#
P1
6
H_A#_10
R16
H_A#_11
N17
H_A#_12
M1
3
H_A#_13
E1
7
H_A#_14
P1
7
M20 CFG_15
L21 CFG_16
H21 CFG_17
P29 CFG_18
R28 CFG_19
P25 CFG_2
T28 CFG_20
P20 CFG_3
P24 CFG_4
C25 CFG_5
N24
0904-00248
9
T25 CFG_0
R25 CFG_1
C24 CFG_10
N21 CFG_11
P21 CFG_12
T21 CFG_13
R20 CFG_14
U7-
1
GL4
0
10
18
15
40
42
43
47
29
39
35
38
25
30
16
1% 22
1
R
58
7
31
21
24
27
13
1
2
1%
2
20
1K R586
0
12
C658
100nF
10V
30
27
28
26
10V
1
P1.05V
100nF
C
65
0
100nF
C632
49
10V
5
6
46
nostuf
f
R602
2.2K
P1.05V
P1.05V
16
28
25
21
37
3
4
5
10
18
33
34
62 61
57
9
11
51
34
29
54
1%
22-D2
55
R584
2K
24
MCH1_H_RCOMP_M
N
MCH1_CFG6_MN
MCH1_VTTLF3_M
N
MCH1_VTTLF2_MN
MCH1_VTTLF1_MN
CPU1_LOCK
#
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
CPU1_TRDY#
CPU1_REQ#(4:0)
CPU1_DPWR
#
MCH1_HVRE
F
MCH1_HXSWIN
G
MCH1_HVRE
F
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
CPU1_D#(63:0)
CPU1_A#(35:3)
CPU1_ADS
#
CPU1_ADSTB0#
CPU1_ADSTB1#
CPU1_BNR
#
CPU1_BPRI#
CPU1_BREQ#
CPU1_SLP#
CPU1_CPURST#
CLK0_HCLK1# CLK0_HCLK
1
CPU1_DBSY# CPU1_DEFER#
CPU1_DBI0#
MCH1_HXSWING
CPU1_DBI1#
CPU1_DBI2#
CPU1_DBI3#
CPU1_DRDY
#
CPU1_DSTBN0#
CPU1_DSTBN1#
CPU1_DSTBN2#
CPU1_DSTBN3#
CPU1_DSTBP0#
CPU1_DSTBP1#
CPU1_DSTBP2#
CPU1_DSTBP3#
CPU1_HIT#
CPU1_HITM#