Block Diagram
6-2
Samsung Electronics
6-2 DLP-Builtin Module
X226
X226 B
(
CP
CPU
&
MP
MPEG.
G. de c ode r
&
Vide o Sc aler
&
OSD
)
TS # A
TS # B
&
Ext
VI DEO
IN # A
Ext
VI DEO
IN #B
Di git al
OUT
AU DIO
OUT
AC 3 /PCM
OU T
T UNE
UNER
#2
(NT )
POD Channel
nnel
(NT & AT SC& QAM )
VIDEO-1
3D-Y
3D-C
VIDEO-2
SUB-V/ Y
SUB-C
RS-232
MICOM_
Rx
MICOM_
Tx
I2C_5V
SDA_M5
SCL _M5
CONTROL
CPU_RESET
Componet-1
COMP1_Y
COMP1_Pb
COMP1_Pr
I2C_M
SDA_M5
SCL_M5
RS-232(Debug)
Rx
Tx
TUNER SIGNAL
M_CVBS
S_CVBS
M_SIF
S_SIF
ADV7400
400
#1
(NT & ADC)
ADV7400
400
#2
(NT & ADC)
HDM
I Rx
TMD
S
Sii9993
HDMI Rx
M
U
X
M
U
X
BA7657
CO M P
S/ W
3D- Y/ C
SUB- Y/ C
S_CV BS
COMP1 Y,Pb,Pr
COMP2 Y,Pb,Pr
3D- Y/ C
SUB- Y/ C
S_CV BS
76 57
Y,Pb,Pr
COMP1 Y,Pb,Pr
COMP2 Y,Pb,Pr
7657 Y,Pb,Pr
PC R,G,B,
HSYNC,VSYNC
CImax
Card I/F
PCMCIA
Cable Card
M
U
X
M
U
X
M
U
X
M
U
X
MU X
HDMI
TMDS
TS_1_DATA[ 7:0]
CLK,VLD,SYNC
TS_2_DATA[7:0]
CLK,VL D,SYNC
D-Flip
-Fl o p
DN
DNIe Pro
Image
Enhancer
TH C63LVDH63
LVDS Tx
OPT ICA L
/RCA
AC 3 /PCM
OU T
I2C
SDA_PANNEL
SCL_PANNEL
LVD
LVDS &
MD_
MD_Contr
ntrol
TX[3:0 ]+-
DLP_SYNCVAL
MD_nRESET
DDP_ READY
PWRGOOD
LVDS_EN
LAM P+Txn,Rx
SDA,SCL PANNEL
AUDIO
I2S_CLK,DATA,LRCLK
NT_I2S_CLK,
DATA,LRCLK
MEMO
MEMORY
(1
(16MB)
B)
K4S643232 x 2
FL
FL ASH
(16 M B)
28 F128
RA
RAM
(128
128 M B)
K4D551638D x2
CL K,VL D,SYNC
TS_A_DATA[ 7: 0]
TS_B_DATA[ 7: 0]
CL K,VL D,SYNC
65 6[7 :0 ] ,CL K
65 6[7 :0 ] ,CL K
AUD
AUDIO
SPDIF
I2S_CL K ,DATA
LR CL K
1 2bi t[ 24: 12 ]
12 bi t
[11 :0 ]
24 bi t
[ 23: 0]
H,V SYNC, CL K 1
H,VSYNC,
CLK
Ext
AUDIO
IN
12 bi t
[11 :0 ]
CLK 0
RS- 232 A
RS- 232 B
MUX
NT _I2S_CL K,
DATA,L RCLK
HDMI_I2S_CLK,
DAT A,L RCLK
MI COM_Rx,T x
Rx,Tx
Scramle TS
UN Scramle TS
or
24 bit[ 7:0],CL K,
HSync,Vsync
DE
Componet-2
COMP2_Y
COMP2_Pb
COMP2_Pr
Содержание HL-R5677W - 56" Rear Projection TV
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