5. System Diagram
5. System Diagram
5.1. Block Diagram
LP EC3
AS IC
En g in e
Co n tro l
DDR2
32b it
SO DIMM
MO DULE
M
U
X
SMPS TYPE5 (STAG E3)
PO WER
CO RD
FUSER La m p Co n tro l
Motor
-O PC BLDC
-DEVE BLDC
-FUSER BLDC
-FEED STEP MO TO R
S ole noid/Clutc h
-CST Pic kup So le noid
-DEVE K Clutc h
- REG I Clutc h
-Fus e r Fa n
-Re a r Fa n
P TB UNIT
ACR s e n s o r L/R
LS U
-2 Po lyg o n Mo tor
-2 Be a m 4 LD
-LSU Te mp
FUS ER UNIT
Th e rmistor1
Th e rmistor2
800W la mp
Th e rmo sta t
500W la mp
S CF UNIT
(OP TION)
HVP S
5
V
5VS
S ATA
US B
HUB
EEP ROM
M24512
WLAN
EDI
Fla s h Me m ory
32M
Co ve r
Switc h
2
4VS1
24V1
S e ns or
-FCF Emp ty
-CST De te c t
-Fe e d Se n s o r
-Exit Se n s o r
-Re g i Se n s or
-P-s ize Se n s o r
Ca s s e tte
-MP Pic kup So le noid
-MP Emp ty Se n s o r
2
4V1/24V2/24V3
5
V_SMPS
DEVICE
US B
RES ET IC
DC Co n ve rte r
Re g u la to r
S C L0_C 4
S DA0_C 4
A
DDR
D
ATA
GIGA BIT
RTL8211D
1W MICO M
n P OWER _OF F
5
V
n KEY_P OWER _S W
n
S LEEP _24V_OF F
S C F _R XD
S C F _TXD
P ANEL_R X
D
P ANEL_TX
D
F US ER C ONTR OL
F US ER B IAS
S C L_B ELT
S DA_B ELT
AN_C TD1_P
AN_C TD2_P
ADC _C TDLED
S e ns or-Ana log
-TEMP_IN
-Humid ity/TEMP_OUT
O UTBIN SENSO R
AC
OP
P a ne l
M
AIN P BA
C
h o ru s
4
O
P TION
DEVE CRUM IF PBA
DEVE Y CRUM
DEVE M CRUM
DEVE C CRUM
DEVE K CRUM
C
LK_LP EC
3
n R ES ET
n F _R ES ET
PWM Co n ’
S
ATA I/F
US B Hos t
DEVICE
US B
3
.3V
1.1V 1.8V
Sys te m
C4 Lp e c 3
VDDQ VTT
1.8.V 0.9V
MCLK
SSCG
UCLK
SATA_CLK
SSCG
RTC CLK
12Mh z
15Mh z
32.768Kh z
12Mh z
VCLK
S
C L_DEV
S DA_DEV
P a ra lle l p wr
CRUM
CTD s e n s or
S UB_AC
-HVPS Fa n
5-1
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