Sailor RE2100, Техническое руководство

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5 CIRCUIT DESCRIPTION AND SCHEMATIC DIAGRAMS RE2100
PAGE 5-13 9406
5.3 SYNTHESIZER UNIT (MODULE 3) PART NO. 625633
The synthesizer unit consists of two phase locked loops. Phase locked loop 1 generates the signal used
as injection to the first mixer in the front end module and as the injection to the second mixer in the exciter
unit. The PLL1 signal has a frequency range from 70 MHz to 100 MHz in steps of 10 Hz.
Phase locked loop 2 generates the injection signal to the first mixer in the exciter unit and the injection
signal to the second mixer in the receiver unit. The PLL2 signal changes between two frequencies 80.7
MHz and 59.3 MHz when the transmitted or received sideband is changed between upper and lower
sideband.
PHASE LOCKED LOOP 1
PLL1 operates as a fractional synthesizer. This means that the dividing figure in the loop can be set to
a non-integer number, making it possible to get a frequency resolution at the VCO output which is smaller
than the reference frequency in the loop. The reference frequency is 40.96 kHz and the frequency
resolution is 10 Hz. The reference frequency is derived from a TCXO, which oscillates at 10.73152 MHz.
Furthermore the TCXO signal is used as carrier signal for both detector in the receiver and SSB generator
in the exciter.
The principle in a fractional synthesizer is that the integer number dividing figure N
i
in the loop is changed
at particular times to (N
i
+1) determined by the value of fraction number F. By this method the mean
frequency of the VCO is increased as illustrated in the example below:
fvco = N x fref
i i
fvco = (N + 0,25) x fref
mean
T=
1
fref
i
fvco = (N + 1) x fref
25740A
In the example the integer dividing figure is changed every fourth reference cycle implying an increase
in mean VCO frequency.
Because of the change in the integer number, dividing figure spurious sidebands occur at the VCO output.
These sidebands have to be reduced and this is done through a correction signal fed to the phase
detector. The correction signal is generated in the API (Analog Phase Interpolator) circuit.
VOLTAGE CONTROLLED OSCILLATORS
The frequency range from 70-100 MHz is covered with four independent oscillators:
VCO I : 70 - 77.5 MHz
VCO II : 77.5 - 85 MHz
VCO III : 85 - 92.5 MHz
VCO IV : 92.5 - 100 MHz
The oscillators are in principle identical and each of them is built-up around an earthed drain FET amplifier,
where the output signal is fed back to the input by means of two capacitors. The ratio of the capacitors
determines the amount of feed-back in the oscillator. The oscillator frequency is determined by the LC
circuit located on the gate of the FET, and the tuning of oscillator frequency is done by means of variable
capacitance diodes.
The output signal from the VCO’s is led through switch diodes D2, D5, D7, and D10 to a common buffer
amplifier Q13, which buffers the VCO signal for prescaler buffer and LO buffer respectively.
Selection of the wanted VCO circuit is done by Q1, Q3, Q4, Q6, Q7, Q9, Q10, and Q12. The control of
these transistors is done by serial to parallel register U1.