Sailor RE2100, Техническое руководство

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5 CIRCUIT DESCRIPTION AND SCHEMATIC DIAGRAMS RE2100
PAGE 5-15 9324
API CIRCUIT
The circuit delivers signal to the modulus control logic and correction signal (API voltage) for the phase
detector. The circuit is built-up around a 12-bit digital accumulator constituted by U2, U3, U4, U7, U8, U9,
and U12 containing a fraction register, a binary adder, and a sum latch.
Overflow information from the binary adder is led to the modulus control logic and implies a change in the
integer number dividing figure in one reference cycle.
In every reference cycle the contents of the accumulator is renewed by clocking the sum latch, the
clocking is controlled by the control logic circuit.
The output from the binary adder is led to a 12-bit D/A converter U14, which in connection with OP. AMP
U18 generates the API voltage.
The reference current to the D/A converter is derived from the reference current to the phase detector
by means of the current mirror and is led through the current switch and current buffer & filter to the D/
A converter.
D11, D12, Q16, and Q15 constitute the current switch, which adjusts the mean value of the reference
current to the D/A converter as a function of the integer number dividing figure in the loop.
When the signal on basis of Q15 is at high state, D11 is switched on and D12 off and vice versa, and by
changing the duty cycle of a square wave signal on basis of Q15 the mean value of the current to the D/
A converter can be adjusted.
Control of the current switch is carried out by the 1/N correction logic, which as a function of the output
from the programmable divider and the output from the prescaler produces a square wave signal
measurable on U13 pin 13 where the duty cycle is varied as function of the integer number loop dividing
figure so that the duty cycle increases for decreasing VCO frequency and vice versa.
From the current switch the current is led to buffer & filter constituted by Q14, C84, and C85, which buffers
and filters out the reference current to the D/A converter.
MODULUS CONTROL LOGIC
The modulus control logic is constituted by U28 and U23, which as a function of overflow signal from the
accumulator, prescaler output, modulus control signal from the programmable divider and output from the
1/N correction logic, generates modulus control signal for the prescaler.
The circuit does not effect the modulus control signal from the programmable divider when the loop
dividing figure includes a fraction part, the prescaler modulus shall be changed in one prescaler output
period from 32 to 33, if there is a reference cycle where overflow signal is given from the digital
accumulator. This change of prescaler modulus implies the needed change of dividing figure to increase
the mean frequency of the VCO with a fraction of the reference frequency, and the change is timed through
the modulus control logic.
DIVIDER CIRCUITS
The programmable divider consists of a dual modulus prescaler U22 dividing by 32/33 and a program-
mable divider included in U24. The integer number dividing figure is latched into U24.
The reference divider consists of a D-FF U31 followed by the programmable reference divider U30.
The division ratio of U31 is 2 and the division ratio of U30 is 131. This implies a total division ratio of 262.
BUFFER CIRCUITS
The VCO signal is led from the VCO buffer into LOl buffer and prescaler buffer.
The LOl buffer consists of Q17 and Q22 and the buffer generates the necessary power level for both
receiver and exciter modules.
The output of the buffer is led to relay RE01, which feeds the signal to receiver and exciter respectively,
dependent upon whether the transceiver is in transmit or receive mode.
The control of RE01 is carried out by serial to parallel register.
The prescaler buffer consists of Q18 and Q21 and the major task of the circuit is to prevent spurious
signals created in the prescaler from being added to the VCO signal and through that imply spectral
impurity of the LOl signal.
The TCXO signal is led to the TCXO buffer, which consists of Q27 and Q26.
The buffer delivers signal for the reference divider and carrier reinjection signal for both receiver and
exciter modules.