Sailor RE2100, Техническое руководство

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5 CIRCUIT DESCRIPTION AND SCHEMATIC DIAGRAMS RE2100
PAGE 5-9 9324
5.2 FRONT END UNIT (MODULE 2) PART NO. 625632
This module consists of a transmit/receive relay and the receiver front end. The front end consists of a
receiver input protection circuit, a radio frequency filter unit, a radio frequency to first intermediate
frequency (70 MHz) mixer, and a first IF (70 MHz) filter unit.
AERIAL/EXCITER SWITCH
The aerial signal enters the receiver through the aerial/exciter socket J01, when relay RE02 is in RX
position. The exciter signal from the power module (8) is connected to relay RE02 through the EX socket
J04. When relay RE02 is in TX position the exciter signal will pass through the aerial/exciter socket J01
and a coax cable to the HF power amplifier in T2130. Switching between RX and TX with RE02 is
controlled from the microprocessor through register U01 and Q02.
INPUT PROTECTION
Protection of the pre-filters and the first mixer is done with R02, R03, TR01 and the circuit around D05,
and it guaranties that the voltages to the pre-filters cannot be higher than about 4.5V. In addition the RX
input is grounded with relay RE01 when the transceiver is switched off.
PRE-FILTERS
The pre-filters consists of the following units:
- 100 kHz HPF consisting of L01-L02 and C08
- 385 kHz LPF (1) consisting of L29, C49-C50 and D16-D17
- 385 kHz - 1.6 MHz BPF (2) consisting of L24-L26, C42-C44 and D14-D15
- 1.6 MHz - 4.5 MHz BPF (3) consisting of L20-L22, C36-C38 and D12-D13
4.5 MHz - 9 MHz BPF (4) consisting of L16-L18, C30-C32 and D10-D11
- 9 MHz - 18 MHz BPF (5) consisting of L12-L14, C24-C26 and D08-D09
- 18 MHz - 30 MHz BPF (6) consisting of L09-L11, C18-C20 and D06-D07
- 30 MHz LPF consisting of L31-L33, and C54-C56
The switching between the filters is controlled from the microprocessor through U01, U02 and U03.
FIRST MIXER AND IF-FILTER
The first mixer is an active J-FET mixer with good, large signal properties and low noise factor.
The signal is led through the balanced transformer TR03 to the sources of the dual J-FET Q04. The first
LO signal from the frequency synthesizer (module 3) is led through the LO buffer (Q03) to give about +17
dBm signal to the gates of the two J-FET transistors. The mixed signals are fed through the balanced
output transformer TR04 to the two high order bilitich crystal filters FL01 and FL02 where the wanted 70
MHz signal is selected. The selected signal is then fed on to the receiver PCB (module 1).