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24
FPGA35S6 User’s Manual
5.5
Digital I/O
The FPGA35S6 digital I/O on connectors CN4 and CN9 use the circuitry shown below to level shift the input voltage from 5V to 3.3V allowing
the I/O on these connectors to be 5V tolerant.
Figure 8: CN4/CN9 Digital I/O Circuitry
Xilinx
Spartan 6
Level Shifter
D
ig
ita
l I
/O
CN4/CN9
33Ω
10KΩ
+5V/3.3V