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FPGA35S6 User’s Manual

JP7: Reserved

JP7 is reserved, and must be left open.

3.3.1

S

OLDER

J

UMPER

B1: Pull up Voltage

Solder jumper B1 are used to set the pull up voltage for JP1, JP2 and JP3.

Table 9: B1 Pull up Voltage

Setting Description

1-2

Sets Pull up voltage to 3.3V

2-3

Sets Pull up voltage to 5V

B2: Pull up Voltage

Solder jumper B1 are used to set the pull up voltage for JP4, JP5 and JP6.

Table 10: B2 Pull up Voltage

Setting Description

1-2

Sets Pull up voltage to 3.3V

2-3

Sets Pull up voltage to 5V

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Содержание FPGA35S6045HR

Страница 1: ...RTD Embedded Technologies Inc AS9100 and ISO 9001 Certified FPGA35S6045HR FPGA35S6100HR FPGA Module User s Manual BDM 610010045 Rev C...

Страница 2: ...RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com...

Страница 3: ...s Inc PS 2 is a trademark of International Business Machines Inc PCI PCI Express and PCIe are trademarks of PCI SIG PC 104 PC 104 Plus PCI 104 PCIe 104 PCI 104 Express and 104 are trademarks of the PC...

Страница 4: ...2 Bus Connectors 14 CN1 Top CN2 Bottom PCIe Connector 14 3 3 3 Jumpers 14 JP1 JP2 JP3 JP4 JP5 JP6 Pull up Pull down Jumper 14 JP7 Reserved 15 3 3 1 Solder Jumper 15 B1 Pull up Voltage 15 B2 Pull up V...

Страница 5: ...1_OUT Write 26 6 1 9 R_PORT1_DIR Read Write 26 6 1 10 R_PORT2L_IN Read 26 6 1 11 R_PORT2L_OUT Write 26 6 1 12 R_PORT2L_DIR Read Write 26 6 1 13 R_PORT2H_IN Read 26 6 1 14 R_PORT2H_OUT Write 26 6 1 15...

Страница 6: ...f Tables Table 1 Ordering Options 8 Table 2 Operating Conditions 9 Table 3 Electrical Characteristics 9 Table 4 CN3 Programming Header 12 Table 5 CN8 I O Pin Assignments 13 Table 6 CN4 I O Pin Assignm...

Страница 7: ...grammable Data Width o Integrated Endpoint block for PCI Express o Integrated Memory Controller 1 Gb of DDR2 SDRAM Supports access rates of up to 800Mb s o Dedicated carry logic for high speed arithme...

Страница 8: ...Embedded Technologies for more information on custom FPGA35S6 products and custom FPGA designs The Intelligent Data Acquisition Node IDAN building block can be used in just about any combination with...

Страница 9: ...t P Power Consumption 1 Vcc5 5 0V 2 5 W Icc 5V Input Supply Current 1 Active 500 mA PCIe 104 Bus Differential Output Voltage 0 8 1 2 V DC Differential TX Impedance 80 120 Differential Input Voltage 0...

Страница 10: ...ou are ready to install it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and us...

Страница 11: ...5S6 User s Manual 3 3 Connectors and Jumpers Figure 2 Board Connections JP4 JP5 JP6 Pull up Pull down Jumper JP1 JP2 JP3 Pull up Pull down Jumper CN3 Programming Header CN1 CN2 PCIe Connector CN8 High...

Страница 12: ...inx JTAG Programming Header Connector CN3 provides a connection to the Xilinx JTAG programming header The pin assignment for CN3 is shown below This connector header mates with the Xilinx OEM programm...

Страница 13: ..._33 input LVDS output is not supported in Bank 1 Table 5 CN8 I O Pin Assignments Port2_n 0 2 1 Port2_p 0 Port2_n 1 4 3 Port2_p 1 Port2_n 2 6 5 Port2_p 2 Port2_n 3 8 7 Port2_p 3 GND 10 9 GND Port2_n 4...

Страница 14: ...9 5V Table 7 CN9 I O Pin Assignments GND 2 1 port1_p 0 JP4 GND 4 3 port1_n 0 GND 6 5 port1_p 1 GND 8 7 port1_n 1 GND 10 9 port1_p 2 GND 12 11 port1_n 2 GND 14 13 port1_p 3 GND 16 15 port1_n 3 GND 18 1...

Страница 15: ...1 are used to set the pull up voltage for JP1 JP2 and JP3 Table 9 B1 Pull up Voltage Setting Description 1 2 Sets Pull up voltage to 3 3V 2 3 Sets Pull up voltage to 5V B2 Pull up Voltage Solder jumpe...

Страница 16: ...perly positioned 6 Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule 7 Hold the module by its edges and orient it so the bus connector pi...

Страница 17: ...our system When removing it from the bag hold the module by the aluminum enclosure and do not touch the components or connectors Handle the module in an antistatic environment and use a grounded workb...

Страница 18: ...r CN4 Pin IDAN P3 Pin Signal Pull Jmpr C9 Pin Row 1 Row 2 Row 3 Row 1 Row 2 Row 3 1 port0_p 0 JP1 1 1 port1_p 0 JP4 1 22 GND 2 22 GND 2 43 port0_n 0 3 43 port1_n 0 3 2 GND 4 2 GND 4 23 port0_p 1 5 23...

Страница 19: ...gital I O Connector Connector Part VALCONN HDB 62S Mating Connector VALCONN HDB 62P Connector P4 provides 40 digital I O lines along with a 5V pin and ground pins These signals are 3 3V tolerant The s...

Страница 20: ...31 32 Port2_n 12 32 53 Port2_p 13 33 12 Port2_n 13 34 33 Port2_p 14 35 54 Port2_n 14 36 13 Port2_p 15 37 34 Port2_n 15 38 55 GND 39 14 GND 40 35 Port2_p 16 41 56 Port2_n 16 42 15 Port2_p 17 43 36 Port...

Страница 21: ...I O signal lines of CN4 and C5 Refer to Table 11 and Table 12 to determine which I O pins are effected by each jumper Table 13 Pull up Pull down Jumper options Setting Description 1 2 I O is pulled up...

Страница 22: ...eripheral cards are connected to the cpuModule 6 Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack 7 Gently and evenly press the mod...

Страница 23: ...r for clock based operations in the FPGA 5 3 EEPROM The FPGA35S6 features a 256 x 16 SPI EEPROM ATMEL AT93C66A For information on the AT93C66A refer to http www atmel com 5 4 DDR2 SRAM The FPGA35S6 fe...

Страница 24: ...FPGA35S6 digital I O on connectors CN4 and CN9 use the circuitry shown below to level shift the input voltage from 5V to 3 3V allowing the I O on these connectors to be 5V tolerant Figure 8 CN4 CN9 D...

Страница 25: ...N 0x34 R_PORT2L_OUT 0x38 R_PORT2L_DIR 0x40 R_PORT2H_IN 0x44 R_PORT2H_OUT 0x48 R_PORT2H_DIR 0x50 R_DDR_RD_DATA 0x54 R_DDR_WR_DATA 0x58 R_DDR_ADDR 0x5C R_DDR_STATUS 0x60 R_CLK_27_1 0x64 R_CLK_27_2 6 1 1...

Страница 26: ...reads the current value the I O 6 1 11 R_PORT2L_OUT WRITE This is the output register for the port2 low port2_ 0 port2_ 15 The value to be output direction must be set to output 6 1 12 R_PORT2L_DIR R...

Страница 27: ...ATUS READ This is a status register for the DDR2 memory interface B0 Read error B1 Read overflow B2 Read empty B3 Read full B4 Write error B5 Write underrun B6 Write empty B7 Write full B 14 8 Read co...

Страница 28: ...t number of modules in the system possible Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorr...

Страница 29: ...pecifications A copy of the latest PC 104 specifications can be found on the webpage for the PC 104 Embedded Consortium www pc104 org 8 2 PCI and PCI Express Specification A copy of the latest PCI and...

Страница 30: ...other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no othe...

Страница 31: ...ologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Copyright 2014 by RTD Embedded Technologies Inc Al...

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