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FPGA35S6 User’s Manual
6.1
BAR0 – FPGA Example Register Map ..................................................................................................................................... 25
6.1.1
R_ID (Read)
25
6.1.2
R_STATUS (Read)
25
6.1.3
R_EEPROM (Read/Write)
25
6.1.4
R_PORT0_IN (Read)
26
6.1.5
R_PORT0_OUT (Write)
26
6.1.6
R_PORT0_DIR (Write)
26
6.1.7
R_PORT1_IN (Read)
26
6.1.8
R_PORT1_OUT (Write)
26
6.1.9
R_PORT1_DIR (Read/Write)
26
6.1.10
R_PORT2L_IN (Read)
26
6.1.11
R_PORT2L_OUT (Write)
26
6.1.12
R_PORT2L_DIR (Read/Write)
26
6.1.13
R_PORT2H_IN (Read)
26
6.1.14
R_PORT2H_OUT (Write)
26
6.1.15
R_PORT2H_DIR (Read/Write)
26
6.1.16
R_DDR_RD_DATA (Read)
26
6.1.17
R_DDR_WR_DATA (Read/Write)
26
6.1.18
R_DDR_ADDR (Read/Write)
26
6.1.19
R_DDR_STATUS (Read)
27
7
Troubleshooting
28
8
Additional Information
29
8.1
PC/104 Specifications ............................................................................................................................................................... 29
8.2
PCI and PCI Express Specification .......................................................................................................................................... 29
9
Limited Warranty
30
