DM5210 analog input module 4-7 RTD Embedded Technologies, Inc.
BA + 8: Read MSB Data/Start 12-Bit Conversion (Read/Write)
A read provides the MSB (8 most significant bits) of the A/D conversion, as defined below. The converted data
is left-justified. When you are performing 8-bit conversions, only the MSB must be read.
Writing to this address starts a 12-bit A/D conversion (the data written is irrelevant).
D7
D6
D5
D4
D3
D2
D1
D0
MSB
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
12-Bit:
8-Bit:
BA + 9: Read LSB Data/Start 8-Bit Conversion (Read/Write)
A read provides the LSB (4 least significant bits) of the A/D conversion, as defined below. The converted data is
left-justified.
Writing to this address starts an 8-bit A/D conversion (the data written is irrelevant).
D7
D6
D5
D4
D3
D2
D1
D0
Bit 3 Bit 2 Bit 1 Bit 0 X X X X
LSB
BA + 10: Read Status/Clear IRQ (Read/Write)
A read provides the two status bits defined below. The end-of-convert bit goes high when a conversion is
complete. The IRQ status bit goes high when an interrupt has occurred and stays high until a clear IRQ command is
sent. The clear IRQ command is sent by writing to BA + 10 (data written is irrelevant).
D7
D6
D5
D4
D3
D2
D1
D0
End-of-Convert
0 = no EOC
1 = conversion done
IRQ Status
0 = No IRQ
1 = IRQ
BA + 11: IRQ Enable (Write Only)
A write enables and disables interrupt generation and interrupt sharing. Writing a “1” to bit 0 enables interrupt
generation; writing a “0” disables interrupt generation, writing a “1” to bit 1 disables interrupt sharing;writing a “0”
enables interrupt sharing. At power up this register is set to "0".
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Enable/Disable
0 = interrupt disabled
1 = interrupt enabled
0
0
0
0
0
0
Interrupt Sharing
0 = enable
1 = disable
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