33/38
TO-247-4L Half-Bridge Evaluation Board
User’s Guide
©
2019 ROHM Co., Ltd.
No. 61UG047E Rev.001
August.2019
14
．
Gate-Source Signal Protection Circuit
This evaluation board is equipped with protection circuits to absorb the surge occurring at the MOSFET Gate-Source pin. The
clamp circuit has three functions and four countermeasure circuits as shown in Table 11. It is important to suppress the surge
voltage by implementing these protection circuits as the Gate-Source voltage is greatly affected by the changes of Vds and Id during
the switching operation. Please note that the Gate-Source voltage behavior is explained in a separate application note (
“Gate-
Source Voltage Behavior in Bridge Configuration (No.60AN135E Rev.001)), it is recommended to refer this application note.
The circuit diagram is shown in Figure 31.
Table 11. Clamp Circuit and Operation Details
Item
Clamp Circuit
Circuit
Symbol
Operation Details
Initial
Setting
(I)
Positive Surge Clamp
D55, C58
The positive side surge that occurs when the Vds change of the
MOSFET is completed. It may exceed the Vgs maximum rating
during turn ON, therefore, D55 will clamp it to Vcc2. C58 is a
bypass capacitor, place its layout close to D55.
No Mount
(II)
Negative Surge Clamp D56, C59
When Vds turns ON at the turn OFF of the opposite MOSFET in a
bridge configuration, a negative surge occurs, and it may exceed
the Vgs negative side maximum rating, therefore, D56 will clamp it
to VEE2. C59 is a bypass capacitor, place its layout close to D56.
No Mount
(III)
Self-turn ON
Surge Clamp
Q53
When the opposite side of the MOSFET in a bridge configuration
turns ON, Vgs gets raised up by the Vds rise, the other MOSFET
turns ON (so-called self-turn ON) when the Vgs exceeded the
threshold voltage. The Vgs rising can be reduced by clamping it
with Q53 (impedance smaller than Gate drive resistor R74). This
countermeasure circuit requires the control signal which generally
included inside the drive IC side. The Q53 is called a miller clamp
MOSFET.
Mount
(IV)
C67
As the Crss/Ciss ratio of the MOSFET increases, Vgs tends to get
raised up easily (as the charging current is proportional to Crss).
The Crss/Ciss ratio can be reduced by adding a capacitor in
parallel to Ciss. It prevents the voltage to exceed the Vth. As the
added capacitance is bigger, the
voltage increase becomes less,
but more drive capability is required and switching loss becomes
higher, so please add the capacitance by considering the heat
dissipation.
No Mount
It is necessary to make these
clamp circuits’ pattern inductances to be as small as possible since the Vgs surge voltage occurs in
several ns, therefore design the layout to be as close as possible to the MOSFET.
Among ROHM SiC MOSFETs, the third generation SCT3xxxx Series has a narrow Gate-Source voltage rating thus, it is
recommended to have these clamp circuits. The Vgs surge voltage can be more effectively suppressed by implementing several of
them on the board, but the priority of the layout to be close to the MOSFET is as follows:
(III)Active Clamp MOSFET
(II)Negative Surge Clamp Circuit
(I)Positive Surge Clamp Circuit
(IV)Additional GS Capacitance (Csg)
Figure 32 shows the protection circuit mounting location.
In addition, the waveform examples with/without the protection circuit are shown in Figure 33
～
34. However, the actual operation
is not only depending on the device itself, but the board where it is mounted also affects the operation greatly, therefore verification
on the actual board is necessary.
HS
LS
