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TO-247-4L Half-Bridge Evaluation Board
User’s Guide
©
2019 ROHM Co., Ltd.
No. 61UG047E Rev.001
August.2019
Connector
Pin
Symbol
I/O
Details
CN201
01
ENABLE
I
Driver ICs U2 and U102 shared Enable pin (individual control is not required)
Active (Driver IC operates) when this signal is Low. It is being
pulled up
with 2.2kΩ resistor at +5V when OPEN.
02
SGND
--
Input signal side GND. It can be completely separated from DUT side GND.
03
IN_CLK
I
ON/OFF signal for HS and LS MOSEFT.
High: HS MOSFET turns ON, LS MOSFET turns OFF.
Low: HS MOSFET turns OFF, LS MOSFET turns ON.
Only valid when connector
「
JP1
」
is set to
“Single-CLK Mode” side. It is being pulled
down with 2.2k
Ω resistor when OPEN.
04
IN_L_CLK
I
ON/OFF signal for LS MOSFET. ON when this signal is High.
Only valid when connector
「
JP1
」
is set to
“Dual-CLK/DP Mode” side. It is being
pulled down with 2.2kΩ resistor when OPEN.
05
SGND
--
Input signal side GND.
06
IN_H_CLK
I
ON/OFF signal for HS MOSFET. ON when this signal is High.
Only valid when connector
「
JP1
」
is set to
“Dual-CLK/DP Mode” side. It is being pulled
down with 2.2kΩ resistor when OPEN.
07
HS_ALOW
I
Logic invert signal for
“IN_H_CLK”. HS MOSFET is ON when this signal is High, and
“IN_H_CLK” signal is Low
It is being pulled down with 2.2kΩ resistor when OPEN.
08
+5Vcc
--
Output pin for control block power supply (+5V). Maximum output is 20mA. Used for
input signal pull-up.
09
LS_ALOW
I
Logic invert signal for “IN_L_CLK”. LS MOSFET is ON when this signal is High, and
“IN_L_CLK” signal is Low.
It is being pulled down with
2.2kΩ resistor when OPEN.
10
SGND
--
Input signal side GND.
CN202
01
Vcc
--
Power supply pin for driver IC and internal control block. Voltage for Gate drive is
generated internally from this power supply.
02
SGND
--
Input signal side GND.
JP1
01
DUAL/DP
I
Signal to set to
“Dual-CLK/DP Mode”. “IN_x_CLK” signal becomes valid when this pin
is Low. It is being pulled up to +5Vcc
with 2.2kΩ resistor when OPEN.
02
SGND
--
Input signal side GND.
03
SINGLE
I
Signal to set to
“Single-CLK Mode”. “IN_CLK” signal becomes valid when
“DUAL/DP“ signal is other than Low.
OPEN condition when it is OPEN.