
Instruction Set
Shift Register
3-34
shift register instructions continued...
Instruction
Description
LIFO Load
LFL
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)
Status Bits:
EN - Enable Load
DN - Done Bit
EM - Empty Bit
When the input conditions go from false-to-true, the processor loads N70:1 into the next
available element in the LIFO file #N70:3, as pointed to by R6:61. Each time the rung goes from
false-to-true, the processor loads another element. When the LIFO file (stack) is full (64 words
have been loaded), the DN bit is set.
LIFO Unload
LFU
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)
Status Bits:
EN - Enable Load
EU - Enable Unload
DN - Done Bit
EM - Empty Bit
When the input conditions go from false-to-true, the processor unloads the last element from
#N70:3 and puts it into N70:2. Each time the rung goes from false-to-true, the processor
unloads another element. When the LIFO file is empty, the EM bit is set.
LIFO LOAD
Source
N70:1
LIFO
#N70:3
Control
R6:61
Length
64
Position
0
LFL
LIFO UNLOAD
LIFO
#N70:3
Dest
N70:2
Control
R6:61
Length
64
Position
0
LFU