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CCT24
3.2 Module Interface
Electrical connections to the CCT24 are made through the I/O pins on the CCT24. The hardware I/O
functions are detailed in the table below:
Pad
Name
I/O
Description
1
PKT_DET
O
Packet detect output. Signal switches logic high at the end of the start-of-packet symbol and switch-
es logic low at the end of the end-of-packet symbol on both received and transmitted packets.
PKT_DET provides a timing reference for use in network timing evaluations, etc.
2
RSVD
-
Reserved pad. Leave unconnected.
3
ADC_REF
I
ADC supply and external full scale reference voltage input. Voltage range is 2.4 to 3.3 Vdc. Connect
pad 34 to this input to reference the ADC full scale reading to the module’s 3.3 V regulated supply.
4
RSVD
-
Reserved pad. Leave unconnected.
5
GPIO0
I/O
Configurable digital I/O port 0. When configured as an input, interrupt from sleep can be invoked.
When configured as an output, the power-on state is also configurable. Sleep mode direction and
state are also configurable.
6
GPIO1
I/O
Configurable digital I/O port 1. Same configuration options as GPIO0.
7
GPIO2
I/O
Configurable digital I/O port 2. Same configuration options as GPIO0.
8
GPIO3
I/O
Configurable digital I/O port 3. Same configuration options as GPIO0, with RS485 driver enable an
alternate function.
9
PWM0
O
8-bit pulse-width modulated output 0 with internal low-pass filter. Filter is 1
st
order, 159 Hz 3 dB BW.
10
PWM1
O
8-bit pulse-width modulated output 1 with internal low-pass filter. Filter is 1
st
order, 159 Hz 3 dB BW.
11
SLEEP/DTR
I
Default functionality is active high module sleep input (active low DTR). When switched low after
sleep, the module executes a power-on reset. Usually connected to host DTR.
12
ADC2
I
10-bit ADC input 0. Full scale reading is referenced to the ADC_REF input.
13
ADC1
I
10-bit ADC input 1. Full scale reading is referenced to the ADC_REF input.
14
ADC0
I
10-bit ADC input 2. Full scale reading is referenced to the ADC_REF input.
15
EX_SYNC
I
Rising-edge triggered input for synchronizing co-located bases. Synchronization pulse interval must
equal the hop dwell time ±10 µs. Pulse width must be in the range of 50 to 800 µs.
16
DIAG_TX
O
Diagnostic UART transmitter output.
17
DIAG_RX
I
Diagnostic UART receiver input.
18
/CFG
I
Protocol selection input. Leave unconnected when using software commands to select transpar-
ent/protocol mode (default is transparent mode). Logic low selects protocol mode, logic high selects
transparent mode.
19
VCC
I
Power supply input, +3.3 to +5.5 Vdc.
20
GND
-
Power supply and signal ground. Connect to the host circuit board ground.
21
GND
-
Power supply and signal ground. Connect to the host circuit board ground.
22
GPIO4
I/O
Configurable digital I/O port 4. When configured as an output, the power-on state is configurable.
The SPI RX data available flag, SPI_RX_AVL, is a configurable alternate function.
23
GPIO5
I/O
Configurable digital I/O port 5. Same configuration options as GPIO4, with antenna diversity control
an alternate function.
24
GND
-
Logic ground.
