Renesas VersaClock7 PCB, Руководство пользователя

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Manual
VersaClock7 PCB Layout Guidelines
R31UH0017EU0100 Rev.1.00
Aug 4, 2022 Page 1
© 2022 Renesas Electronics
PCB layout is a physical realization of the circuit designs. Good board layout practices will improve the electrical
performance by controlling crosstalk and ensuring signal integrity. In addition, layout plays a fundamental role in
meeting EMC emissions and immunity requirements.
This document provides information and recommendations to aid in the design and layout of PCB circuitry using
VersaClock7 (VC7) devices. It contains information for generic PCB layout and some particular considerations
for VC7 devices.
Contents
1. Layer Stack-Up ............................................................................................................................................... 2
2. Placement ....................................................................................................................................................... 4
3. Crystal Placement and Handling .................................................................................................................. 4
4. VC7 Device Electrical and Thermal Pad Handling...................................................................................... 5
4.1 RC21008A/RC31008A – 40-LGA
[3]
...................................................................................................... 5
4.2 RC21012A/RC21012A – QFN-48
[4]
...................................................................................................... 7
4.3 RC21005A/RC21005AQ – 32-LGA
[5]
.................................................................................................... 8
5. Trace Routing ................................................................................................................................................. 9
5.1 Single-Ended Routing ............................................................................................................................ 9
5.2 Differential (Clock) Pair Routing ............................................................................................................ 9
6. Power Supply Trace and Power Filtering Layout ..................................................................................... 12
7. References .................................................................................................................................................... 13
8. Revision History .......................................................................................................................................... 13