
RSK+RX71M
6. Configuration
R20UT3217EG0100 Rev. 1.00
Page 53 of 71
Jan 23, 2015
6.18
QSPI Configuration
below details the function of the option links associated with QSPI configuration.
Signal name
MCU
MCU Peripheral Selection
Destination Selection
Pin
Po
rt
Signal
Fit
DNF
Interface
Function
Fit
DNF
ET0RXCLK
_REF50CK0_QSSL-A
85 P76
REF50CK0
J8.Pin1-2,
R58
R50
U6.70, X5.3 R62, R63 R26, R64,
R68
ET0RXCLK
J8.Pin1-2,
R50
R58
U6.79
R57
-
BD_QSSL-A
J8.Pin2-3,
R386
R392
U8.1
-
-
TFT_QSSL-A
J8.Pin2-3,
R392
R386
TFT.32
-
-
ET0RXER_RMII0RXER
_QSPCLK-A 84 P77
ET0RXER_RMII0RXER
SW6.9.ON
SW6.10.OFF U6.2
-
-
BD_QSPCLK-A
SW6.10.ON,
R382
SW6.9.OFF,
R381
U8.6
-
-
TFT_QSPCLK-A
SW6.10.ON,
R381
SW6.9.OFF,
R382
TFT.29
R232
-
ET0TXEN_RMII0TXDEN
_QIO2-
A_MTIOC3B
81 P80
ET0TXEN_RMII0TXDEN SW7.1.ON
SW7.2.OFF,
SW7.3.OFF U6.13
R32
-
QIO2-A
SW7.2.ON
SW7.1.OFF,
SW7.3.OFF
U8.3
-
-
MTIOC3B
SW7.3.ON
SW7.1.OFF,
SW7.2.OFF
JA2.13
-
-
ET0ETXD0_RMII0TXD0
_QIO3-
A_MTIOC3D
80 P81
ET0ETXD0_RMII0TXD0 SW7.4.ON
SW7.5.OFF,
SW7.6.OFF U6.14
R31
-
QIO3-A
SW7.5.ON
SW7.4.OFF,
SW7.6.OFF
U8.7
-
-
MTIOC3D
SW7.6.ON
SW7.4.OFF,
SW7.5.OFF
JA2.14
-
-
A19_ET0TXER_QIO0-A_MTIOC4D
83 PC3
A19_ET0TXER_QIO0-
A_MTIOC4D
-
-
JA3.40
-
-
ET0TXER
SW5.6.ON
SW5.7.OFF,
SW5.8.OFF JA3.40, T26
-
-
BD_QIO0-A
SW5.7.ON,
R375
SW5.6.OFF,
SW5.8.OFF,
R374
JA3.40,
U8.5
-
-
TFT_QIO0-A
SW5.7.ON,
R374
SW5.6.OFF,
SW5.8.OFF,
R375
JA3.40,
TFT.31
R234
-
MTIOC4D
SW5.8.ON
SW5.6.OFF,
SW5.7.OFF
JA3.40,
JA2.18
-
-
A20_ET0TXCLK_QIO1-A_POE0n
82 PC4
A20_ET0TXCLK_QIO1-
A_POE0n
R345
-
JA3.41
-
-
ET0TXCLK
R345,
SW5.9.ON
SW5.10.OFF JA3.41,
U6.12
R33
-
BD_QIO1-A
R345,
SW5.10.ON,
R371
SW5.9.OFF,
R370, R372
JA3.41,
U8.2
-
-
TFT_QIO1-A
R345,
SW5.10.ON,
R370
SW5.9.OFF,
R371,
R372
JA3.41,
TFT.30
R225
-
POE0n
R345,
SW5.10.ON,
R372
SW5.9.OFF,
R370,
R371
JA3.41,
JA2.24
-
-
Table 6-35: QSPI Option Links
Содержание RX71M
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