8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 6
2. Input/Output Interface
2.1
Input Termination for Reference Clock Input
The 8V19N850 reference clock input CLK/nCLK is a high impedance differential receiver. The inverting input
nCLK has weak bias to ~1.65V. The input can accept a signal from a standard 3.3V LVPECL or an LVDS driver
directly in DC coupling. The board-level termination at the CLK/nCLK input is determined by the driver type.
Figure 4 and Figure 5 provide examples of input interface without AC coupling. Figure 6 and Figure 7 provide
examples of input driven by a differential driver with AC coupling. This section provides only few examples.
Other termination topologies can also be used. For single-ended driving the differential input, please refer to the
example in the OX_DPLL Input (OCXO/TCXO) input section.
Figure 4. Input Term ination Exam ple – 8V19N850 Reference Clock Input CLK/nCLK, Driven by a 3.3V LVPECL Driver
Figure 5. Input Term ination Exam ple – 8V19N850 Reference Clock Input CLK/nCLK Driven by a 3.3V LVDS Driver
Clock Input
CLK
nCLK
VCC=3.3V
R4
82.5
R2
82.5
R3
133
R1
133
VCC=3.3V
Zo = 50
Zo = 50
LVPECL Driv er
VCC=3.3V
VCC=3.3V
Zo = 50
Zo = 50
LVDS Driv er
VCC=3.3V
R1
100
Clock Input
CLK
nCLK
