Renesas 8V19N850, Руководство пользователя

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Guide
8V19N850 Hardware Design
X0120307 Rev.1.0
Mar 25, 2021 Page 1
© 2021 Renesas Electronics
This document contains general board-level hardware design information for the 8V19N850. It provides
recommendations for power rail handling, loop filter calculation, and input/output termination.
Contents
1. Power Rails .................................................................................................................................2
1.1 Bypass Capacitors ................................................................................................................2
1.2 Power Supply Isolation ..........................................................................................................3
1.3 Loop Filter ...........................................................................................................................3
1.4 2
nd
Order Loop Filter .............................................................................................................3
1.5 Loop Filter Calculation Examples ............................................................................................5
2. Input/Output Interface ..................................................................................................................6
2.1 Input Termination for Reference Clock Input .............................................................................6
2.2 OX_DPLL Input (OCXO/TCXO) ..............................................................................................7
2.3 OSCI/OSCO Input (XTAL, XO, OCXO/TCXO) ...........................................................................8
2.4 Output Terminations for QCLK and QREF Drivers .....................................................................9
2.4.1. LVPECL Type Driver Terminations .............................................................................9
2.4.2. LVDS Type Driver Terminations ............................................................................... 14
3. Schematic Example ................................................................................................................... 15
4. Revision History ........................................................................................................................ 15
The simplified block diagram of 8V19N850 is shown in Figure 1. For a more detailed block diagram and in-depth
descriptions about the device, see the
8V19N850 Datasheet .
Figure 1. Sim plified Block Diagram
A general reference schematic example is shown in Figure 2. A larger version can also be provided in a
separate document. In this schematic, the input and output interfaces are shown for illustration purposes. For
more examples, see the Input/Output Interface section. The input topology depends on the driver type, and the
output driver termination depends on the receiver specification and structure.