8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 9
Figure 10. Single-ended Oscillator Overdrive OSCI Exam ple
Notes:
1. When OSCI or XO_DPLL is used for input of APLL0 or APLL1 with DPLL0 or DPLL1 active, the selected
frequency cannot cause the APLL0 or APLL1 feedback divider to set to an integer. For example, if APLL0
VCO
= 2.5GHz, OSCI = 50MHz, the APLL0 PDF = 2x50MHz = 100MHz, the APLL0 feedback must be set to
25. The feedback divider = 25 is an integer. If DPLL0 is not active, there is no issue. If DPLL0 is active, this
will create a problem and cause DPLL0 to be unstable; therefore, a 50MHz oscillator cannot be used under
this condition.
2. When both XO_DPLL and OCSI are used, the two frequencies should not be close to each other.
The following list shows a few examples of OCXO:
■
Rakon U7842 or different frequency in the same product family.
■
TXC OG48070001 or different frequency in the same product family.
■
CTS17 or different frequency in the same product family.
2.4
Output Terminations for QCLK and QREF Drivers
The output stage of the 8V19N850 QCLK drivers can be configured to be LVPECL style driver or LVDS style
driver.
2.4.1. LVPECL Type Driver Terminations
When the 8V19N850 output is configured to LVPECL, the driver is an open emitter type that requires a DC
current path to the termination voltage V
TT
through the pull-down resistor. A standard LVPECL driver termination
is shown in Figure 10, and Figure 12 to Figure 14 show alternative terminations. The LVPECL output driver is
configurable and the applicable termination voltage V
TT
depends on the output amplitude setting and output
supply voltage V
DDO_v
. Refer to the V
TT
and termination resistor value tables below each diagram.
C1
Zo
R3
R2
100
R1
100
Ro
8V19N850 OSCI input
OSCI
OSCO
VDD
OCXO/TCXO LVCMOS
