Renesas 8V19N850, Руководство пользователя

Страница: 5 / 16

8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021 Page 5
1.5 Loop Filter Calculation Examples
This section provides calculation examples for APLL0 loop filter value for loop bandwidth of ~150kHz. In this
example, the reference OCXO input frequency = 48MHz after multiplied by 2, the phase detector input frequency
Fpd = 96MHz. This satisfies the condition of Fpd/Fc >> 20.
The APLL0 VCO frequency, Fvco = 2500MHz, the effective feedback divider.
N = Mv = Fvcxo / Fpd ~ 26
Rs can be calculated from the equation,
𝑅𝑅𝑅𝑅 =
2 ∗
π
∗ fc ∗ N
Icp ∗ Kvco
The APLL0 VCO gain, Kvco ~30MHz/V.
The charge pump current is set as 1.7mA in this example.
Rs = 510 Ohm
Cs can be calculated from the following equation,
𝐶𝐶𝑅𝑅 =
α
2 ∗ 𝜋𝜋 ∗ 𝑓𝑓𝑓𝑓 ∗ 𝑅𝑅𝑓𝑓
For α
= 10, Cs is calculated to be ~20 nF. Cs
greater than this value can be used to assure that the α is greater
than 10. For example, the actual chosen value can be 100 nF from a standard capacitor value to allow room for
charge pump current adjustment.
Cp can be calculated from the equation,
𝐶𝐶𝐶𝐶 =
Cs
α ∗ β
For β
= 3, Cp is calculated to be ~650pF. Less than this value can
be used for Cp to assure that the β is greater
than 3 (e.g., the actual selected value Cp can be 470 nF).
Phase margin = 67 degrees
The following table shows Loop Filter Value Examples for APLL0, APLL1, APLL2, and RFPLL. The loop filter
values will vary based on the application requirement. Other loop values can also be used as long as the PLLs
operate at the stable region.
Table 2. 8V19N850 Analog PLLs Loop Filter Values Exam ples
APLL0 APLL1 APLL2 RFPLL
Loop Bandw idth (Hz) 150k 600k 80k 80k
PDF 96MHz 96Mhz 78.125MHz 245.76MHz
Feedback divider, N 26 40 48 24
Charge Pump current
setting
Can be set betw een 0.7mA
to 2.2mA
1.7mA 1.7mA 1.7mA 1.7mA
Rs (Ohm ) 510 2k 300 200
Cs 100nF 100nF 100nF 100nF
Cp 470pF ~33pF ~33pF ~33pF