User’s Manual
GSM35
29
RTD Finland Oy
Saving the Startup Interrupt Mask Register (IMR) and interrupt vector
The next step after writing the ISR is to save the startup-state of the
interrupt mask register, (IMR) and the original interrupt vector you are
using. The IMR is located in address 21h. The interrupt vector you will be
using is located in the interrupt vector table which is an array of pointers
(addresses) and it is locate din the first 1024 bytes of the memory
(Segment 0 offset 0). You can read this value directly, but it is better
practice to use DOS function 35h (get interrupt vector) to do this. Most C
compilers have a special function available for doing this. The vectors for
the hardware interrupts on the XT - bus are vectors 8-15, where IRQ0 uses
vector 8 and IRQ7 uses vector 15. Thus if your GSM35 is using IRQ5 it
corresponds to vector number 13.
Before you install your ISR, temporarily mask out the IRQ you will be using.
This prevents the IRQ from requesting an interrupt while you are installing
and initializing your ISR. To mask the IRQ, read the current IMR at I/O port
21h, and set the bit that corresponds to the IRQ. The IMR is arranged so
that bit 0 is for IRQ0 and bit 7 is for IRQ7. See the paragraph entitled
Interrupt Mask Register (IMR
) earlier in this discussion for help in
determining your IRQ's bit. After setting the bit, write the new value to I/O
port 21h.
With the startup IMR saved and the interrupts temporarily disabled, you
can assign the interrupt vector to point to your ISR. Again you can
overwrite the appropriate entry in the vector table with a direct memory
write, but this is not recommended. Instead use the DOS function 25h (Set
Interrupt Vector) or, if your compiler provides it, the library routine for
setting up interrupt vectors. Remember that interrupt vector 8 corresponds
to IRQ0, vector 9 for IRQ1 etc.
If you need to program the source of your interrupts, do that next. For
example, if you are using transmitted or received messages as an interrupt
source program it to do that. Finally, clear the mask bit for your IRQ in the
IMR. This will enable your IRQ.
Common Interrupt mistakes
Remember hardware interrupts are from 8-15, XT IRQ's are numbered 0-7.
Do not forget to clear the IRQ mask bit in the IMR Forgetting to send the
EOI command after ISR code. Disables further interrupts.
