Copyright © 2015 Robot Circuits, LLC
32
RCAT-1A Rev A3 Designer’s manual
Serious Power for the Serious Designer
USART 1 Port – J6
Connector J6 allows direct access to CPU ports PD2 and PD3 (via J6) if the USART 1 functions are not in use.
These connections can be routed through the 3.3Vdc to 5Vdc level translators in similar fashion to USARTs 2 and
3 as described earlier.
Refer to Figure 32 below:
Schematic
Figure 32
With shunts installed on JP6 across pins A-B and on JP15 across pins A-B, you gain direct connection from J6 pin
1 to CPU port PD3. Refer to the bold orange lines in Figure 32.
With shunts installed on JP7 across pins A-B and on JP17 across pins A-B, you gain direct connection from J6 pin
2 to CPU port PD2. Refer to the bold blue lines in Figure 32.
As with USARTS 2 and 3 described earlier, J6 can be routed through the 3.3Vdc to 5Vdc level translators in
transit from J6 to/from the CPU chip.
Routing of J6 through the level translators is similar to the above USARTS, but there are a couple of twists to
consider.
