Copyright © 2015 Robot Circuits, LLC
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RCAT-1A Rev A3 Designer’s manual
Serious Power for the Serious Designer
Ports PL0 and PL1 are a special case. They are shared with the control of the mosfet driver subsystem shown here:
Figure 8
As shown in the diagram on the left, from the CPU chip, ports PL0 and PL1 are connected on the board to the gates of
mosfets Q3 and Q4. However, they are also brought out to connector J5 via a pair of jumpers as shown in the right-hand
diagram. This enables you to control the gates either from the CPU via software or externally, by configuring ports PL0
and/or PL1 as inputs, and installing JP28 and/or JP29, thus bringing connection to the gates out to J5.
The third and final type of subsystem on the RCAT™ board is what we call a “bussed” subsystem. The primary system of
this type is the two-wire-interface (TWI) subsystem. Consider the following schematic:
Figure 9
Here we can see that CPU ports SCL(PD0) and SDA(PD1) interface with the onboard 1M-bit serial EEPROM (U3). But then
the ports are also connected to pullup resistors R5/R5 and then broken out for external access to J2 so that you have
direct access to the TWI subsystem as well.
