User Manual for Microboard Computer Development System CDP18S693 & CDP18S694
40
The CPU monitors these data transfers, going into an
S2 machine state for each byte transfer. R0 is used as
the memory pointer and is automatically incremented
each time. Thus, DMA transfers are interleaved with
normal processing and no software action is required
except to initialize R0 before transfer starts. INT
and/ or an EF may be used to notify the program that a
block DMA transfer is completed so that initialization
and processing of the data block may be performed.
The DMA inputs may be maintained in the true state
for contiguous S2 states for the most rapid transfer. In
the usual case, however, the DMA request is removed
at the TPA of the S2 cycle to obtain a single byte
transfer, allowing time for normal processing and for
setting up the next byte in the requesting controller.
Each S2 state is eight clock cycles in duration.
SC1, SCO
—State code outputs from the CPU which
identify the type of machine cycle in progress.
State CodeLines
State Type
SC1
SCO
S0 (Fetch)
L
L
S1
(Execute)
L
H
S2 (DMA)
H
L
S3
(Interrupt)
H
H
CLOCK OUT—
A
2-M H z
square-w ave clock
provided for general use. It is derived fromthecrystal-
controlled oscillator in the CPU
WAIT, CLEAR—
-Two control inputs to the CPU
which determine the mode of operation.
CLEAR
WAIT
Mode
L
L
Load
L
H
Reset
H
L
Pause
H
H
Run
The functions of the modes are defined as follows:
Load Mode.
Holds the CPU in the IDLE state and
allows an I/O device to load the memory without the
need for a “bootstrap” loader. It modifies the IDLE
condition so that term ination of the DMA-IN
operation does not force execution of the next
instruction. DMA in requests then load memory
starting from location zero for as many bytes as there
are DMA-IN requests.
Reset Mode.
Registers I, N, and Q are reset, IE is set,
and 0’s (Vss) are placed on the data bus. TPA and TPB
are suppressed while reset is held and the CPU is
placed in S 1. The first machine cycle after termination
of reset is an initialization cycle which requires 9 clock
pulses. During this cycle the CPU remains in S1, and
registers X, P, and R0 are reset. Interrupt and DMA
servicing are suppressed during the initialization cycle.
The next cycle is an S0 or an S2, but never an S3.
Power-up reset is obtained by a Schm itt-trigger
buffered RC network connected to CLEAR.
Pause Mode.
Stops the internal CPU timing
generator on the first high-to-low transition of the
input clock. The oscillator continues to operate, but
subsequent clock transitions are ignored.
Run Mode.
May be initiated from the Pause or
Reset Mode functions. If initiated from Pause, the
CPU resumes operation on the first high-to-low
transition of the input clock. If initiated from Reset,
the first machine cycle following Reset is always the
initialization cycle. The initialization cycle is then
followed by a DMA (S2) cycle or fetch (S0) from
location 0000 in memory.
RNU—Run Utility Software. A signal supplied to
the system to force the most significant address line
true. As a result, the program start is at memory
location 8000 instead of 0000. The CDP18S652
Microboard provides the Reset and Run Modes for
the System.
